CD2231 Intel Corporation, CD2231 Datasheet - Page 58

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
58
The receive bit rate generator can also be programmed to act as a DPLL . In that mode, the clock
select and divisor are programmed to be as near as possible to the nominal receive bit rate. Clock
phase adjustments are made by the DPLL logic to lock to the incoming datastream. The receive bit
clock is an optional input to the transmitter. This makes it possible to use the DPLL-derived clock
to synchronize the transmit datastream.
Section 5.2
given bit rate is determined with:
The above equation, in general, yields a non-integer result. The nearest integer value, along with
the clock source, is the optimum choice for that bit rate. The value loaded in the Period register
must be that integer expressed as an 8-bit binary value. The bit-rate error is the difference between
the integer value and the ideal value, expressed as a percentage.
Example 1
This example illustrates programming the bit rate generator at 19.2 kbits/second using the internal
clock, at a system clock frequency of 33 MHz.
Divisor loaded into R(T)BPR = 214 or d6h
Value loaded into R(T)COR = 00h, to select Clk 0
Example 2
This example illustrates programming the bit rate generator at 56,000 bps using external clock, at a
system clock frequency of 33 MHz.
The user provides a 1.25-MHz clock on the RXCIN or TXCIN pin.
Divisor loaded into R(T)BPR = 21 or 15h
Value loaded into RCOR = 06h, to select External Clock mode
Value loaded into TCOR = C0h, to select External Clock mode
includes examples for programming standard bit rates. The value to be loaded to set a
Bit rate divisor
Frequency of chosen clock source
------------------------------------------------------------------------------------------
Desired bit rate
=
–
1
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