CD2231 Intel Corporation, CD2231 Datasheet - Page 90

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.2.2
8.2.2.1
90
Register Name: COR1
Register Description: Channel Option Register 1
Default Value: x’00
Access: Byte Read/Write
AFLO
Bit 7
Channel Option Register 1 (COR1)
COR1 — HDLC Mode
If any options specified in this register are changed, an initialize command must be given to
CD2231 through the Channel Command register.
Bit 7
Bit 6
Bits 5:4
Bits 3:0
ClrDet
Bit 6
Address field length option
0 = Address field is 1 octet in length
1 = Address field is 2 octets in length
Clear detect for X.21 data transfer phase
0 = Clear detect disabled
1 = Clear detect enabled
A clear is defined as two consecutive all-zero receive characters with the CTS* pin
high.
Addressing modes
00 = no address recognition
01 = 4 * 1 byte
10 = 2 * 2 byte
If this bit is set, RFAR1, RFAR2, RFAR3, and RFAR4 should contain the address
to be matched. If AFLO is set to ‘1’, an address match is made against the RFAR1
and RFAR2 pair or the RFAR3 and RFAR4 pair.
Inter-frame flag option
Defines the minimum number of flags transmitted before a frame is started.
The minimum number of opening flags always precede a frame when idle in Mark
mode is set, or is always separated by two consecutively transmitted frames. No
restriction is placed on the number of flags between received frames.
AdMd1
Bit 5
Flags 3
0
0
1
Flags 2
through
AdMd0
0
0
1
Bit 4
Flags 1
0
0
1
Flag3
Bit 3
Flags 0
0
1
1
Flag2
Bit 2
minimum of 1 opening flag, with shared
closing/opening flags permitted
minimum number of opening flags sent
Motorola Hex Address: x’10
Flag1
Bit 1
Intel Hex Address: x’13
Datasheet
Flag0
Bit 0