Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet
Z8FMC160100KITG
Specifications of Z8FMC160100KITG
Related parts for Z8FMC160100KITG
Z8FMC160100KITG Summary of contents
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... An Company ® Z8 Encore! Motor Control Flash MCUs Z8FMC16100 Series Product Specification PS024613-0910 ® Copyright ©2010 by Zilog , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, and eZ80 are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS024613-0910 ...
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Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate links given in the table below. Revision Date Level September 13 2010 August ...
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Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Interrupt Control Register ...
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PWM Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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I C Master/Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Sample Settling ...
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Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Introduction Zilog’s Z8FMC16100 Series Flash MCU is based on Zilog’s advanced eZ8 8-bit CPU core and is optimized for motor control applications. It supports control of single and multiphase variable speed motors. Target applications are consumer appliances, HVAC, factory automation, refrigeration, and automotive applications. ...
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Block Diagram Figure 1 displays the architecture of the Z8FMC16100 Series Flash MCU Port A 8 Port B 1 Port C 6 Figure 1. Z8FMC16100 Series Flash MCU Block Diagram PS024613-0910 Analog Supply and Reference UART with LIN ...
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... CPU and Peripheral Overview Zilog’s latest 8-bit eZ8 CPU meets the continuing demand for faster and more code- efficient microcontrollers. The eZ8 CPU executes a superset of original Z8 set. The eZ8 CPU features include: • Direct register-to-register architecture allows each register to function as an accumulator, improving execution time, and decreasing the required program memory • ...
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Analog Comparator The Z8FMC16100 Series Flash MCU features an on-chip analog comparator with external input pins. Operational Amplifier The Z8FMC16100 Series Flash MCU features a two-input and one-output operational amplifier. General-Purpose Input/Output The Z8FMC16100 Series Flash MCU features 17 GPIO ...
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Inter-Integrated Circuit 2 The I C controller makes the Z8 Encore! MCU compatible with the I controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL) line. The I arbitration. Internal Precision Oscillator ...
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PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification On-Chip Debugger 6 ...
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Signal and Pin Descriptions The Z8FMC16100 Series Flash MCU products are available in various package styles and pin configurations. This chapter describes the signals and available pin configurations for each package style. For more information on the physical package specifications, ...
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Signal Descriptions Table 1 describes the Z8FMC16100 Series Flash MCU signals. Table 1. Signal Descriptions Signal Mnemonic I/O Description General-Purpose Input/Output Ports A–H PA[7:0] I/O Port A[7:0]: These pins are used for general-purpose I/O. PB[7:0] I/O Port B[7:0]: These pins ...
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Table 1. Signal Descriptions (Continued) Signal Mnemonic I/O Description Analog ANA[7:0] I Analog Input: These signals are inputs to the ADC. V I/O Voltage buffer output: This signal provides reference voltage for external REF components. Caution If using the internal ...
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Table 1. Signal Descriptions (Continued) Signal Mnemonic I/O Description Power Supply Power Supply Ground Pin Characteristics Table 2 lists the characteristics for each Z8FMC16100 Series Flash MCU’s 32 ...
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... The Data Memory contains addresses for all the memory locations that hold data only. For more information on the eZ8 CPU and its address space, refer to eZ8 CPU User Manual (UM0128), available for download at www.zilog.com. Register File The Z8FMC16100 Series Flash MCU supports up to 512 B of internal RAM within the Register File address space. The Register File is composed of two sections— ...
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Program Memory The Z8FMC16100 Series Flash MCU products contain on-chip Flash Memory in the Program Memory address space, depending upon the device (FMC08100 has 8 KB and FMC04100 has 4 KB). Reading from Program Memory addresses outside ...
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Table 4. Z8FMC16100 Series Information Area Map Program Memory Address (Hex) FE00h–FE3Fh FE40h–FE5Fh FE60h–FFFFh PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification Function Reserved. Part Number 20-character ASCII alphanumeric code Left justified and filled with zeros (ASCII Null character). Reserved. 13 ...
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PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification Information Area 14 ...
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Register File Address Map Table 5 provides the address map for the Register File of the Z8FMC16100 Series Flash MCU. Table 5. Register File Address Map Address (Hex) Register Description General Purpose RAM—Z8FMC16 devices with 512 B On-Chip RAM 000–1FF ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description F27 PWM Output Control Register F28 PWM Fault Control Register F29 Current Sense ADC Trigger Control Register F2A–B Reserved F2C PWM High Byte Register (PWMH) F2D PWM Low Byte ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description LIN-UART F40 LIN-UART Transmit Data Register LIN-UART Receive Data Register F41 LIN-UART Status 0 Register F42 LIN-UART Control 0 Register F43 LIN-UART Control 1 F44 LIN-UART Mode Select and ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description F63 SPI Mode Register F64 SPI Diagnostic State Register F65 Reserved F66 SPI Baud Rate High Byte Register (SPIBRH) F67 SPI Baud Rate Low Byte Register (SPIBRL) F68–F6F Reserved ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description FC4 IRQ1 Enable High Bit Register (IRQ1ENH) FC5 IRQ1 Enable Low Bit Register (IRQ1ENL) FC9–FCE Reserved FCF Interrupt Control Register GPIO Port A FD0 Port A Address FD1 Port ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description Trim FF6 Trim Bit Address Register FF7 Trim Bit Data Register Flash Memory Controller FF8 Flash Control Register Definitions FF8 Flash Status Register FF9 Flash Page Select Register FF9 ...
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Reset and Stop Mode Recovery The Reset Controller within the Z8FMC16100 Series Flash MCU controls RESET and Stop Mode Recovery operation. In typical operation, the following events cause a RESET to occur: • Power-On Reset • Voltage Brownout (VBO) • ...
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System Reset During a system reset, the Z8FMC16100 Series Flash MCU is held in RESET for 66 cycles of internal precision oscillator (IPO). At the beginning of RESET, all GPIO pins are configured as inputs. All GPIO programmable pull-ups are ...
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Power-On Reset Each device in the Z8FMC16100 Series Flash MCU contains an internal Power-On Reset (POR) circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating ...
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After the supply voltage again exceeds the POR voltage threshold and stabilized, the device progresses through a full System Reset sequence, as described in the Power-on reset section. Following POR, the POR status bit in the Reset Source register is ...
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Reset state. If the RESET pin is held Low beyond the System Reset timeout, the device exits the Reset state 16 system clock cycles following RESET pin deassertion. If the RESET pin is released ...
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The eZ8 CPU fetches the Reset vector at Program Memory addresses and loads that value into the Program Counter. Program execution begins at the Reset vector address. Following Stop Mode Recovery, the STOP bit in the trol Register is set ...
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Reset Control Register Definitions Writing the 14h unlocks access to the bit. The following sequence is required to unlock this register and write the 1. Write to the Reset Status and Control register (RSTSTAT). 14h 2. Write to the Reset ...
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Table 10. Reset Status Register Values following Reset Reset or Stop Mode Recovery Event Power-On Reset Reset using RESET pin assertion Reset using Watchdog Timer timeout Reset by OCD writing OCDCTL[ Reset from Fault Detect Logic Stop Mode ...
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Low-Power Modes The Z8FMC16100 Series Flash MCU products contain power saving features. The highest level of power reduction is provided by STOP mode. The next level of power reduction is provided by the HALT mode. STOP Mode Executing eZ8 CPU’s ...
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Program counter (PC) stops incrementing • WDT’s internal RC oscillator continues to operate • If enabled, the WDT continues to operate • All other on-chip peripherals continue to operate The eZ8 CPU can be brought out of HALT mode ...
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Bit Position Value (H) Description [7:5] Must be 0. Reserved [4] VBO Detector Disable VBODIS (This bit and the VBO_AO Option Bit must be enabled for the VBO to be active). 0 VBO Detector is enabled. 1 VBO Detector is ...
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PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification Power Control Register 0 32 ...
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General-Purpose Input/Output The Z8FMC16100 Series Flash MCU contains general-purpose input/output pins (GPIO) arranged as Ports A–C. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, pull-up, and alternate pin functions. Each ...
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On-Chip Peripheral System Clock Port Output Control Port Output Data Register Data Bus D Q System Clock Port Data Direction Figure 5. GPIO Port Pin Block Diagram GPIO Alternate Functions Many GPIO port pins can be used as both GPIO ...
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Alternate function settings affect the pins direction (output enable) and muxes the output data that come from the peripheral instead of GPIO. The input path coming from the pad to a peripheral is not blocked based on the alternate function ...
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Table 13. Port Alternate Function Mapping (Continued) Port Pin Mnemonic Port A PA1 PA1 OPINP and CINN PA0 PA0 OPINN Port B PB7 PB7 ANA7 PB6 PB6 ANA6 PB5 PB5 ANA5 PB4 PB4 ANA4 PB3 PB3 PB3INT ANA3 and OPOUT ...
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Table 13. Port Alternate Function Mapping (Continued) Port Pin Mnemonic Port B PB2 PB2 PB2INT ANA2 T0IN2 PB1 PB1 PB1INT ANA1 PB0 PB0 PB0INT ANA0 Port C PC0 PC0 T0OUT GPIO Interrupts Many GPIO port pins can be used as ...
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GPIO Control Register Definitions Four registers for each Port provide access to GPIO control, input data, and output data. Table 14 lists these Port registers. Use the Port A–C Address and Control registers together to provide access to subregisters for ...
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Port A-C Address Registers The Port A–C Address registers select the GPIO port functionality accessible through the Port A–C Control registers. The Port A–C Address and Control registers combine to provide access to all GPIO port control. See Table 15. ...
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Port A–C Control Registers The Port A–C Control registers (PxCTL) set the GPIO port operation. The value in the corresponding Port A–C Address register determines the control subregisters accessible using the Port A–C Control registers to all subregisters that configure ...
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Bit Position Value (H) Description [7:0] These bits control the direction of the associated port pin. Port Alternate Data Direction Function operation overrides the Data Direction register setting. 0 Output. Data in the Port A–C Output Data register is driven ...
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Table 19. Port A–B Alternate Function 0 Subregisters BITS 7 6 AF0_7 AF0_6 FIELD 0 0 RESET R/W R/W R/W If 02H in Port A-C Address register, accessible through the Port A-C Control register ADDR Bit Position Value (H) Description ...
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Port A–C High Drive Enable Subregisters The Port A–C High Drive Enable subregisters C Control registers by writing the Port A–C High Drive Enable subregisters to 1 configures the specified port pins for high current output drive operation. The Port ...
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Bit Position Value (H) Description [7:0] Port STOP Mode Recovery Source Enable PSMRE 0 The Port pin is not configured as a STOP Mode Recovery source. Transitions on this pin during STOP mode do not initiate STOP Mode Recovery. 1 ...
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Port A Interrupt Edge Select Subregister The Interrupt Edge Select (IRQES) Subregister is generated for the rising edge or falling edge on the selected GPIO Port A input pin. Table 24. Interrupt Edge Select Subregister (IRQES) BITS 7 6 Reserved ...
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Port B Alternate Function 1 Subregisters The Port B Alternate Function Subregisters Control register by writing tion subregister selects the alternate functions for the selected pins. To determine the alter- nate function associated with each port pin, see Caution: Do ...
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Bit Position Value (H) [7:0] PIN 0 1 Port A–C Output Data Registers The Port A–C Output Data registers contain the data to be driven out from the port pins. The values are only driven if the cor- responding pin ...
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PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification Port A–C Output Data Registers 48 ...
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... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information on interrupt servicing by the eZ8 CPU, refer to eZ8 CPU User Man- ual (UM0128), available for download at www.zilog.com. Interrupt and System Exception Vector Listing Table 29 lists the SEs and the interrupts in order of priority ...
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Table 29. Reset, System Exception, and Interrupt Vectors in Order of Priority Program Memory Vector Base Programmable Priority Address Reset and System Exceptions 0002h 0004h 003AH 003CH 0006h Interrupts (maskable) Highest 0008h 000Ah 000Ch 000Eh 0010h 0012H 0014H 0016H 0018H ...
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Port Interrupts Internal Interrupts System Exceptions Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions: • Execution of an Enable ...
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... LDX command and the last LDX command are lost. The following code segment is an example of a poor coding style which results in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK Q0 avoid missing interrupts, Zilog in the Interrupt Request 0 register: ANDX IRQ0, MASK PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification Table 29. ® ...
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... The following code segment is an example of a poor coding style that results in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0 avoid missing interrupts, Zilog in the Interrupt Request registers: ORX IRQ0, MASK Interrupt Control Register Definitions The interrupt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests ...
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Bit Position Value (H) Description [7] PWM Timer Interrupt Request PWMI 0 No interrupt request is pending for the PWM interrupt request from the PWM is awaiting service. [6] Fault Interrupt Request. The fault interrupt is generated in ...
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If the interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt Request 1 register to determine if any interrupt requests are pending. Table 31. Interrupt Request 1 Register (IRQ1) BITS 7 6 I2CI Reserved FIELD 0 0 ...
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Bit Position Value (H) Description [0] PA4 or PA0 Interrupt Request—Logic in the Port A GPIO module selects PA40I either PA4 or PA0 and either rising or falling edge interrupt request is pending for PA4 or PA0 1 ...
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Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL) BITS 7 6 PWMENL FLTENL FIELD 0 0 RESET R/W R/W R/W ADDR PWMENL—PWM Interrupt Request Enable Low Bit FLTENL—Fault Interrupt Request Enable Low Bit ADCENL—ADC Interrupt Request Enable Low Bit CMPENL—Comparator ...
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Bit Position Name Description [7] I2CENH I2C Interrupt Request Enable High Bit [5] PC0ENH Port C0Interrupt Request Enable High Bit [4] PBENH Port B[3:0] Interrupt Request Enable High Bit [3] PA73ENH Port A73 Interrupt Request Enable High Bit [2] PA62ENH ...
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Table 38. Interrupt Control Register (IRQCTL) BITS 7 6 IRQE FIELD 0 0 RESET R/W R R/W ADDR IRQE—Interrupt Request Enable This bit is set execution (Enable Interrupts) or IRET (Interrupt Return) instruction, or ...
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PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification Interrupt Control Register 60 ...
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Watchdog Timer The Watchdog Timer (WDT) helps protect against corrupted or unreliable software and other system-level problems which may place the Z8FMC16100 Series Flash MCU into unsuitable operating states. The WDT includes the following features: • On-chip RC oscillator • ...
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Table 39. Watchdog Timer Approximate Timeout Delays WDT Reload Value (Hex) 0400 FFFF Watchdog Timer Refresh When first enabled, the WDT is loaded with the value in the Watchdog Timer Reload reg- isters. The WDT then counts down to eZ8 ...
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WDT Reset in Normal Operation If configured to generate a Reset when a timeout occurs, the WDT forces the device into the Reset state. The WDT status bit in the more information on Reset and the page 21. Following a ...
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Table 40. Watchdog Timer Reload High Byte Register (WDTH) BITS 7 6 FIELD RESET R/W ADDR R/W* - Read returns the current WDT count value. Write sets the appropriate Reload Value. WDTH—WDT Reload High Byte Most significant byte (MSB), Bits[15:8], ...
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Pulse Width Modulator The Z8FMC16100 Series Flash MCU includes a Pulse-Width Modulator (PWM) optimized for Motor Control applications. The PWM features include: • 6 independent PWM outputs or 3 complementary PWM output pairs • Programmable deadband insertion for complementary output ...
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Figure 7 displays the architecture of the PWM modulator. 12-Bit Counter with Prescaler PWM Deadband PWMH0D Data Bus System Clock PWML0D PWMH1D PWML1D PWMH2D PWML2D PWM Option Bits To protect the configuration of critical PWM parameters, the settings to enable ...
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PWM Off State and Output Polarity The default OFF state and the polarity of the PWM outputs are controlled by the and option bits. The PWMLO PWM High outputs H0, H1, and H2. The polarity for the Low outputs L0, ...
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PWM Prescaler The prescaler allows the PWM clock signal to be decreased by factors with respect to the system clock. The (PWMCTL1) controls prescaler operation. This 2-bit prescale value only changes upon a PWM ...
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PWMHx No Dead Band PWMLx PWMHx Dead Band Insertion PWMLx EDGE-ALIGNED Mode In EDGE-ALIGNED PWM mode, a 12-bit up counter creates the PWM period with a minimum resolution equal to the PWM clock source period. The counter counts up to ...
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PWM Duty Cycle Registers The PWM Duty Cycle registers (PWMH0D, PWML0D, PWMH1D, PWML1D, PWMH2D, and PWML2D) contain a 16-bit signed value, in which bit 15 is the sign bit. The Duty Cycle value is compared to the current 12-bit unsigned ...
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PWM Deadband register (PWMDB). The minimum deadband duration is one system clock, and the maximum duration is 255 system clocks. During the deadband period, ...
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PWM Timer and Fault Interrupts The PWM generates interrupts to the eZ8 CPU on any of the following events: PWM Reload— The interrupt is generated at the end of PWM period, when a PWM register reload occurs (the PWM Fault— ...
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PWM Operation in CPU Halt Mode When eZ8 CPU is operating in HALT mode, the PWM continues to operate, if enabled. To minimize the current in HALT mode, the PWM must be disabled by clearing the PWMEN bit to 0. ...
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Table 43. PWM Low Byte Register (PWML) BITS 7 6 FIELD RESET R/W ADDR PWMH and PWML—PWM High and Low Bytes These 2 bytes, {PWMH[3:0], PWML[7:0]}, contain the current 12-bit PWM count value. PWM Reload High and Low Byte Registers ...
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Table 45. PWM Reload Low Byte Register (PWMRL) BITS 7 6 FIELD RESET R/W ADDR PWMRH and PWMRL—PWM Reload Register High and Low These two bytes form the 12-bit Reload value, {PWMRH[3:0], PWMRL[7:0]}. This value sets the PWM period. PWM ...
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Table 47. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL, PWMLxDL) BITS 7 6 FIELD RESET R/W ADDR Bit Position Value (H) Description [7] Duty Cycle Sign SIGN 0 Duty Cycle is a positive two’s complement number. 1 Duty ...
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Bit Position Value (H) Description [7] Place PWM outputs in off-state PWMOFF 0 Disable modulator control of PWM pins. Outputs are in predefined off- state. This is not dependent on the reload event. 1 Re-enable modulator control of PWM pins ...
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PWM Control 1 Register The PWM Control 1 (PWMCTL1) register operation. Table 49. PWM Control 1 Register (PWMCTL1) BITS 7 6 RLFREQ[1:0] FIELD 00 RESET R/W R/W ADDR Bit Position Value (H) [7:6] RLFREQ[1: [5] INDEN ...
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Bit Position Value (H) [1:0] PRES PWM Deadband Register The PWM Deadband (PWMDB) register value. This register determines the number of system clock cycles inserted as dead-time in complementary output mode. The minimum deadband value is ...
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A Value other than 00H must be written to the PWMMPF register or the PWM output wave- Caution: form will be distorted. Table 51. PWM Minimum Pulse Width Filter (PWMMPF) BITS 7 6 FIELD RESET R/W ADDR Bit Position Value ...
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Bit Position Value (H) Description [7:6] Must be 0. Reserved [5] Debug Entry Fault Mask DBGMSK 0 Entering CPU DEBUG mode generates a PWM fault. 1 Entering CPU DEBUG mode does not generate a PWM fault. [4:3] Must be 0. ...
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Table 53. PWM Fault Status Register (PWMFSTAT) BITS 7 6 RLDFlag Reserved DBGFLAG FIELD U 0 RESET R/W1C R R/W ADDR Bit Position Value (H) Description [7] Reload Flag RLDFlag This bit is set and latched when a PWM timer ...
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PWM Fault Control Register The PWM Fault Control (PWMFCTL) register recovers from a fault condition. Settings in this register select automatic or software controlled PWM restart. Table 54. PWM Fault Control Register (PWMFCTL) BITS 7 6 Reserved DBGRST Fault1INT ...
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Bit Position Value (H) Description [2] Comparator 0 Restart CMP0RST 0 Automatic recovery. PWM resumes control of outputs when all fault sources have deasstered all fault sources have deasserted and all fault flags are cleared and a PWM ...
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Bit Position Value (H) Description [5:0] Sample PWM pins IN2H/IN2L/ Low level signal was read on the pins. IN1H/IN1L/ High level signal was read on the pins. IN0H/IN0L PWM Output Control Register The PWM Output Control ...
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An ADC conversion will be triggered on the rising edge of this signal. The logic equation for the adc-trigger is: ADCTRIGGER = CSTPOL ^ ( where • the ^ symbol ...
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Bit Position Value (H) Description [7] 0 Sample Hold Polarity CSTPOL Hold when terms are active 1 Hold when terms are not active [6] 0 High Side Active enable HEN Ignore Product of PWMH0, PWMH1, and PWMH2 in Sample/Hold equation ...
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PS024613-0910 Z8FMC16100 Series Flash MCU Product Specification Current Sense ADC Trigger Control Register 88 ...
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General-Purpose Timer The Z8FMC16100 Series Flash MCU contains one 16-bit reloadable timer used for timing, event counting, or generation of PWM signals. Features The features of general-purpose timer include: • 16-bit reload counter • Programmable prescaler with prescale values from ...
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Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The general-purpose timer is a 16-bit up-counter. In normal operation, the timer is initial- ized to . After it is enabled, the timer counts up to the ...
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Timer Operating Modes The timers can be configured to operate in the following eleven modes: • ONE-SHOT mode • TRIGGERED ONE-SHOT mode • CONTINUOUS mode • COUNTER mode • COMPARATOR COUNTER mode • PWM SINGLE OUTPUT mode • PWM DUAL ...
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If using the Timer Output alternate function, set the initial output level (High or Low) using the (e) Set the interrupt mode. 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. ...
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If using the Timer Output alternate function, set the initial output level (High or Low) via the (e) Set the INTERRUPT mode. 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. ...
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Write to the Timer High and Low Byte registers to set the starting count value (usually ). This setting only affects the first pass in CONTINUOUS mode. After the first 0001h timer reloads in CONTINUOUS mode, counting begins at ...
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Follow the steps below to configure a timer for COUNTER and COMPARATOR COUNTER modes and initiate the count: 1. Write to the Timer Control registers to: (a) Disable the timer. (b) Configure the timer for COUNTER or COMPARATOR COUNTER mode. ...
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Follow the steps below to configure a timer for either PWM SINGLE or DUAL OUTPUT mode and initiate PWM operation: 1. Write to the Timer Control registers to: (a) Disable the timer. (b) Configure the timer for the selected PWM ...
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If TPOL is set to 1, the ratio of the PWM output High time to the total period is determined by the equation: PWM Output High Time Ratio (%) = CAPTURE Modes There are three capture modes that provide slightly ...
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Timer High and Low Byte registers is reset to resumes capture event occurs, upon reaching the compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte ...
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Follow the steps below to configure a timer for COMPARE mode and initiate the count: 1. Write to the Timer Control registers to: (a) Disable the timer. (b) Configure the timer for COMPARE mode. (c) Set the prescale value. (d) ...
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Follow the steps below for configuring a timer for GATED mode and initiating the count: 1. Write to the Timer Control registers to: (a) Disable the timer. (b) Configure the timer for GATED mode. (c) Set the prescale value. (d) ...
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If either the Timer High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low Byte) at the next clock edge. The counter continues counting from the new value. Table ...
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Timer 0 Reload High and Low Byte Registers The Timer 0 Reload High and Low Byte (T0RH and T0RL) registers Table 61) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte register are stored ...
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Timer 0 PWM High and Low Byte Registers The Timer 0 PWM High and Low Byte (T0PWMH and T0PWML) registers, shown in Table 62 63, define PWM operations. These registers also store the timer counter values for the Capture modes. ...
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Timer 0 Control Registers Two Timer 0 control registers determine timer configuration (T0CTL0) and operation (T0CTL1). Timer 0 Control 0 Register The Timer 0 Control 0 (T0CTL0) register together with the Timer 0 Control 1 (T0CTL1) register, determines the timer ...
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Bit Position Value (H) [4] TINSEL 0 1 [3–1] PWMD 000 001 010 011 100 101 110 111 [0] INCAP 0 1 Timer 0 Control 1 Register The Timer 0 Control 1 (T0CTL1) register prescaler value, and determines the timer ...
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Bit Position Value (H) Description [6] Timer Input/Output Polarity TPOL This bit is a function of the current operating mode of the timer. It determines the polarity of the input and/or output signal. When the timer is disabled, the Timer ...
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Bit Position Value (H) Description [5:3] The timer input clock is divided by 2 PRES to 7. The prescaler is reset each time the Timer is disabled. This insures proper clock division each time the Timer is restarted. 000 Divide ...
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Bit Position Value (H) Description [2:0] This field along with the TMODE[3] bit in T0CTL0 register determines the TMODE[2:0] operating mode of the timer. TMODE[3:0] selects from the following modes: 0000 0001 ONE-SHOT mode 0010 CONTINUOUS mode 0011 COUNTER ...
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LIN-UART The Local Interconnect Network Universal Asynchronous Receiver/Transmitter (LIN- UART full-duplex communication channel capable of handling asynchronous data transfers in standard UART applications as well as providing LIN protocol support. Features of the LIN-UART include: • 8-bit asynchronous ...
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RxD TxD CTS DE Data Format for Standard UART Modes The LIN-UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even- or odd-parity bit or multiprocessor address/data bit can be optionally added to the ...
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Idle State lsb of Line 1 Start Bit 0 0 Figure 12. LIN-UART Asynchronous Data Format without Parity Idle State lsb of Line 1 Start Bit 0 Bit 1 0 Figure 13. LIN-UART Asynchronous Data Format with Parity Transmitting Data ...
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Check the TDRE bit in the LIN-UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a ...
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The LIN-UART is now configured for interrupt-driven data transmission. As the LIN- UART Transmit Data register is empty, an interrupt is generated immediately. When the LIN-UART Transmit interrupt is detected, and there is transmit data ready to send, the associated ...
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Read data from the LIN-UART Receive Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the Multiprocessor Mode bits 7. Return to Step 5 Receiving Data using Interrupt-Driven Method The LIN-UART Receiver interrupt ...
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The LIN-UART is now configured for interrupt-driven data reception. When the LIN- UART Receiver interrupt is detected, the associated ISR performs the following: 1. Check the LIN-UART Status 0 register to determine the source of the interrupt-error, break, or received ...
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DE 0 Idle State lsb of Line 1 Start Bit 0 0 Figure 14. LIN-UART Driver Enable Signal Timing The Driver Enable to 1 Baud Rate (Hz) LIN-UART Special Modes The special modes of the LIN-UART are: • MULTIPROCESSOR ...
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The character format is given below. Idle State lsb of Line 1 Start Bit 0 Bit 1 0 Figure 15. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the MULTIPROCESSOR control ...
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UART interrupts to go inactive until the next address byte. If the new frame’s address matches the LIN-UART’s, then the data in the new frame is processed. The second scheme is enabled by setting address into the LIN-UART Address Compare ...
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In LIN mode, the interrupts defined for normal UART operation still apply with the following changes. • Parity Error ( bit. The PLE UART is transmitting. This applies to both Master and Slave operating modes. • The Break Detect interrupt ...
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In the LIN Slave mode, the moves through the Wait For Break, AutoBaud, and Active states. The Noise Filter may also need to be enabled and configured when interfacing to a LIN bus. LIN MASTER Mode Operation LIN MASTER ...
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If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must be detected by a GPIO edge detect Stop Mode Recovery. The duration of the Stop Mode Recovery sequence may preclude making an accurate ...
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When Active State (autobaud has completed), a Break more bit times is recognized and will cause a transition to the Autobaud state. If the Identifier character indicates ...
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LIN-UART Overrun Errors When an overrun error condition occurs the LIN-UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until the valid data has been read. ...
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Read data Figure 16. LIN-UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the bit of the Multiprocessor Control register (LIN-UART Control 1 register BRGCTL with MSEL = 000b UART Receiver interrupt asserts when the LIN-UART Baud Rate ...
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LIN-UART Baud Rate Generator The LIN-UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The LIN-UART Baud Rate High and Low Byte registers combine ...
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The digital filter output features hysteresis. • Provides an active low Saturated State output ( presence of noise. Architecture Figure 17 displays how the noise filter is integrated with the LIN-UART for use on a LIN network. System Clock ...
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Baud Period System Clock Input RxD (ideal) Data Bit = 0 Noise Filter ...
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LIN-UART Control Register Definitions The LIN-UART control registers support the LIN-UART, the associated Infrared Encoder/ Decoder and the noise filter. For more information on the infrared operation, see Encoder/Decoder LIN-UART Transmit Data Register Data bytes written to the LIN-UART Transmit ...
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LIN-UART Status 0 Register The LIN-UART Status 0 register identifies the current LIN-UART operating configuration and status. Table 68 page 130 describes the Status0 register for LIN mode. Table 68. LIN-UART Status 0 Register – Standard UART Mode (U0STAT0) BITS ...
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Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0) BITS 7 6 RDA PLE FIELD 0 0 RESET R R R/W ADDR Receive Data Available (RDA)— received data. Reading the Receive Data register clears this bit. Physical Layer Error ...
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LIN-UART Mode Select and Status Register The LIN-UART Mode Select and Status register status bits. A more detailed discussion of each bit follows the table. Table 70. LIN-UART Mode Select and Status Register (U0MDSTAT) BITS 7 6 MSEL FIELD 0 ...
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The current byte is not the first data byte of a new frame. The current byte is the first data byte of a new frame. MPRX—Multiprocessor Receive Returns the value of the last multiprocessor bit received. ...
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LIN-UART Control 0 Register The LIN-UART Control 0 register UART’s transmit and receive operations. A more detailed discussion of each bit follows the table. Table 71. LIN-UART Control 0 Register (U0CTL0) BITS 7 6 TEN REN FIELD 0 0 RESET ...
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In LIN mode, the master sends a Break character by asserting of the break is timed by hardware, and the Break is ...
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Address Compare register and on all successive data bytes until an address mismatch occurs. The LIN-UART generates an interrupt request on all received data bytes for which the most recent address byte matched ...
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Noise Filter Control Register When MSEL = 001b digital noise filter. Table 73. Noise Filter Control Register (U0CTL1 with MSEL = 001b) BITS 7 6 NFEN FIELD 0 0 RESET R/W R/W R/W ADDR NFEN—Noise Filter Enable Noise ...
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LIN Control Register When = MSEL 010b operation. Table 74. LIN Control Register (U0CTL1 with MSEL = 010b) BITS 7 6 LMST LSLV FIELD 0 0 RESET R/W R/W R/W ADDR LMST—LIN Master Mode LIN Master Mode not ...
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Autobaud state (only valid for LSLV = 1) Active state (either LMST or LSLV may be set) TxBreakLength—Used in LIN mode by the master to control the duration of the trans- mitted Break. ...
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LIN-UART data rate is calculated using the following equation for standard UART modes. For LIN protocol, the Baud Rate registers must be programmed with the Table 76. LIN-UART Baud Rate High Byte Register (U0BRH) BITS 7 6 FIELD RESET ...
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For a given LIN-UART data rate, the integer baud rate divisor value is calculated using the following equation for standard UART operation: UART Baud Rate Divisor Value For a given LIN-UART data rate, the integer baud rate divisor value is ...
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Table 79. LIN-UART Baud Rates, 10.0 MHz System Clock BRG Applicable Divisor Actual Rate Rate (kHz) (Decimal) (kHz) 1250.0 N/A N/A 625.0 1 625.0 250.0 3 208.33 115.2 5 125.0 57.6 11 56.8 38.4 16 39.1 19.2 33 18.9 Table ...
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Table 81. LIN-UART Baud Rates, 3.579545 MHz System Clock (Continued) BRG Applicable Divisor Actual Rate Rate (kHz) (Decimal) (kHz) 57.6 4 55.9 38.4 6 37.3 19.2 12 18.6 Table 82. LIN-UART Baud Rates, 1.8432 MHz System Clock BRG Applicable Divisor ...
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... RxD Infrared TxD Encoder/Decoder (endec) Baud Rate Clock pin. The data received from the infrared transceiver is TXD pin, decoded by the infrared endec, and passed RXD Z8FMC16100 Series Flash MCU Product Specification Zilog ZHX1810 RxD RxD TxD TxD Infrared Transceiver Architecture 143 ...
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UART. Communication is half-duplex, which means simultaneous data transmis- sion and reception is not allowed. The baud rate is set by the UARTs Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. ...
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Receiving IrDA Data Data received from the infrared transceiver via the IR_RXD signal through the decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is used by the infrared endec to generate the demodulated ...
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If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits for next falling edge. As each ...
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Serial Peripheral Interface The Serial Peripheral Interface (SPI synchronous interface allowing several SPI-type devices, such as EEPROMs interconnected. The SPI features include: • Full-duplex, synchronous, character-oriented communication • Four-wire interface • Data transfer rates up to ...
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To Slave # Pin To Slave # Pin From Slave To Slave To Slave Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System From Master To Master From Master From Master ...
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Operation The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (serial clock, transmit, receive, and slave select). The SPI block consists of a transmit/receive shift register, a Baud Rate (clock) Generator, and a control unit. During ...
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The master drives the serial clock through its own serial clock (SCK) pin to the slave’s SCK pin. When the SPI is configured as a slave, the SCK pin is an input and the clock signal from the ...
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Table 83. SPI Clock Phase and Clock Polarity Operation PHASE Transfer Format Phase Equals Zero Figure 25 displays the timing diagram for an SPI transfer in which The two SCK waveforms show polarity with CLKPOL reset ...
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Transfer Format Phase Equals One Figure 26 displays the timing diagram for an SPI transfer in which forms are depicted for SCK, one for CLKPOL reset to 0, and another for CLKPOL set to 1. SCK (CLKPOL = 0) SCK ...
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Slave Operation The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and the MMEN bit the SPICTL register and setting the SSIO bit the SPIMODE register. The ...
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The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous transaction suspended. Writing SPI Interrupts When SPI interrupts are enabled, the SPI generates an interrupt after character transmission/reception is completed in ...
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SPI Data Register The SPI Data register stores both the outgoing (transmit) data and the incoming (receive) data. Reads from the SPI Data register always return the current contents of the 8-bit shift register. Data is shifted out starting with ...
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IRQE—Interrupt Request Enable 0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller. SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller. STR—Start an SPI Interrupt Request ...
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SPI Status Register The SPI Status register indicates the current state of the SPI. All bits revert to their reset state if the SPIEN bit in the SPICTL register = 0. Table 86. SPI Status Register (SPISTAT) BITS 7 6 ...
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SLAS—Slave Select If SPI enabled as a Slave, input pin is asserted (Low) input is not asserted (High). If SPI enabled as a Master, this bit is not applicable. SPI Mode Register The SPI ...
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SSIO—Slave Select I/O pin configured as an input. pin configured as an output (MASTER mode only). SSV—Slave Select Value If SSIO = 1 and SPI configured ...
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SPI Baud Rate High and Low Byte Registers The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value (BRG[15:0]) for the SPI Baud Rate Generator. The SPI baud rate is calculated using the following ...
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I C Master/Slave Controller 2 The I C Master/Slave Controller ensures that the Z8FMC16100 Series Flash MCU devices are bus-compatible with the I signal (SDA) and a serial clock signal (SCL) bidirectional lines. The features of I controller include: ...
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SDA SCL I2CISTAT Interrupt Figure 27 Master/Slave Controller Registers Table 91 summarizes the I PS024613-0910 Z8FMC16100 Series Flash MCU Baud Rate Generator I2CBRH I2CBRL Tx/Rx State Machine I2CCTL I2CMODE I2CSLVAD Register Bus 2 ...
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Table 91 Master/Slave Controller Registers Name Data Interrupt Status Control Baud Rate High Baud Rate Low State 2 I ...
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The ACKV bit in the I2CSTATE register enables the master to check the Acknowledge from the slave before sending the next byte. • Support for multimaster environments—if arbitration is lost when operating as a master, the ARBLST bit in ...
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I C Interrupts 2 The I C controller contains multiple interrupt sources that are combined into one interrupt request signal to the interrupt controller. If the I interrupt is determined by which bits are set in the I2CISTAT register. ...
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General Call/STARTBYTE address. The automatically when the I2CISTAT register is read. If configured through the addressing, the most significant 7 bits of the first byte of the transaction are compared against the SLA[6:0] ...
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Start and Stop Conditions The master generates the START and STOP conditions to start or end a transaction. To start a transaction, the I nal Low while SCL is High. To complete a transaction, the I condition by creating a ...
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Master Arbitration If a master loses arbitration during the address byte, it releases the SDA line, switches to SLAVE mode and monitors the address to determine selected as a slave master loses arbitration during the ...
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The transaction field labels are defined as follows: S Start W Write A Acknowledge A Not Acknowledge P Stop Master Write Transaction with a 7-Bit Address Figure 28 displays the data transfer format from a master to a 7-bit addressed ...
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The I C slave sends an Acknowledge (by pulling the SDA signal Low) during the next High period of SCL. The I If the slave does not acknowledge the address byte, the I 2 bit in the I ...
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Read/Write control bit (which is cleared to 0). The transmit operation is performed in the same manner as 7-bit addressing. The procedure for a master transmit operation to a 10-bit addressed slave is as follows: 1. The software initializes the ...
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The I C controller shifts out the remainder of the second byte of the slave address (or ensuing data bytes, if looping) via the SDA signal. 2 16. The I C slave sends an Acknowledge by pulling the ...
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The I C controller sends The I C controller sends the address and Read bit out via the SDA signal The I C slave acknowledges the address by pulling the SDA signal Low ...
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The software asserts the IEN bit in the I Control register. 2. The software writes 0 (write) to the I 3. The software asserts the 2 4. The I C controller ...
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STOP tion is complete, and the following steps can be ignored. 2 16. The I C controller sends a repeated 2 17. The I C controller loads the I register (the third address transfer). 2 18. The I ...
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The I C controller automatically responds during the Acknowledge phase with the value in the NAK General Call and Start Byte Address Recognition— address phase, and the controller is configured for MASTER/SLAVE or SLAVE in either 7- or ...
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Slave Receive Transaction with 7-Bit Address The data transfer format for writing data from a master to a slave in 7-bit address mode is shown in Figure operating as a slave in 7-bit addressing mode and receiving data from the ...
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The master sends the 2 cause the I C controller to assert a STOP interrupt (the register). Because the slave received data from the master, the software takes no action in response to the STOP interrupt other than reading ...
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The I C controller receives the first byte and responds with Acknowledge or Not Acknowledge, depending on the state of the controller generates the receive data interrupt by setting the register. 7. The software responds by reading the ...
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When the master initiates the data transfer, the I controller holds SCL Low until the software has written the first data byte to the I2CDATA register. 4. SCL is released and the first data byte is ...
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The software configures the controller for operation as a slave in 10-bit addressing mode: (a) Initialize the or MASTER/SLAVE mode with 10-bit addressing. (b) Optionally set the (c) Initialize the I2CMODE register. (d) Set IEN 2. The master initiates ...
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The bus cycles through steps until the final byte has been transferred. If the software has not yet loaded the next data byte when the master brings SCL Low to transfer the most significant data bit, ...
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Table 93 Interrupt Status Register (I2CISTAT) BITS 7 6 TDRE RDRF FIELD 1 0 RESET R R R/W ADDR TDRE—Transmit Data Register Empty 2 When the I C Controller is enabled, this bit is 1 when the ...
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SPRS—Stop/Restart Condition Interrupt This bit is set when the I RESTART condition during a transaction directed to this slave. This bit clears when the I2CISTAT register is read. Read the whether the interrupt was caused by a STOP or RESTART ...
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STOP—Send Stop Condition When set, this bit causes the I STOP condition after the byte in the I a byte has been received in a receive operation. When set, this bit is reset by the I Controller after a STOP ...
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The I C baud rate is calculated using the following equation: Note use BRG 0000h Baud Rate (bps Table 95 Baud Rate High Byte Register (I2CBRH) BITS 7 ...
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When the DIAG on the internal state of the I each bit follows this table. When the DIAG controller state machine 2 Table 97 State Register (I2CSTATE) - Description when DIAG = 0 BITS 7 6 ACKV ACK ...
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BUSY—I C Bus Busy activity on the transaction is underway on the I 2 Table 98 State Register (I2CSTATE) - Description when DIAG = 1 BITS 7 6 I2CSTATE_H FIELD ...