Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 216

KIT DEV FOR Z8 ENCORE Z8FMC16100

Z8FMC160100KITG

Manufacturer Part Number
Z8FMC160100KITG
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphical User Interface
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4660
Table 108. Sample and Settling Time (ADCSST)
BITS
FIELD
RESET
R/W
ADDR
PS024613-0910
Bit Position
[7:5]
[4:0]
SST
Sample Settling Time Register
Sample Time Register
7
The Sample Settling Time register
the SAMPLE/HOLD signal to the START signal, when the conversion can begin. The 
number of clock cycles required for settling varies from system to system depending on the
system clock period used. You must program this register to contain the number of clocks
required to meet a 0.5 µs minimum settling time.
The Sample Time register
sample after a conversion has begun by setting the START bit in the ADC Control register
or initiated by the PWM. The number of system clock cycles required for sample time varies
from system to system, depending on the clock period used. You must program this register
to contain the number of system clocks required to meet a 1 µs minimum sample time.
Value (H)
0H–FH
0H
Reserved
R
6
0
Description
Reserved—Must be 0.
Sample settling time in number of system clock periods to meet 0.5
minimum.
5
(Table
109) is used to program the length of active time for the
(Table
4
1
F74H
108) is used to program the length of time from
3
1
Z8FMC16100 Series Flash MCU
SST
R/W
2
1
Sample Settling Time Register
Product Specification
1
1
µ
s
0
1
204

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