Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 69

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL)
Table 36. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS024613-0910
IRQ1 Enable High and Low Bit Registers
PWMENL
I2CENH
R/W
R/W
7
0
7
0
PWMENL—PWM Interrupt Request Enable Low Bit
FLTENL—Fault Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
CMPENL—Comparator Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
The IRQ1 Enable High and Low Bit registers, shown in
priority encoded enabling for interrupts in the Interrupt Request 1 register. Priority is 
generated by setting bits in each register.
Table 35. IRQ1 Enable and Priority Encoding
0
0
1
1
Note: x indicates the register bits from 0 through 7
IRQ1ENH[x] IRQ1ENL[x] Priority
Reserved
FLTENL
R/W
R
6
0
6
0
ADCENL
PC0ENH
0
1
0
1
R/W
R/W
5
0
5
0
Disabled
Level 1
Level 2
Level 3
CMPENL
PBENH
R/W
R/W
4
0
4
0
FC2H
FC4H
Table 35
PA73ENH PA62ENH PA51ENH PA40ENH
T0ENL
R/W
.
R/W
Description
Disabled
Low
Nominal
High
3
0
3
0
describes the priority control for IRQ1.
Z8FMC16100 Series Flash MCU
IRQ1 Enable High and Low Bit Registers
U0RENL
Table 36
R/W
R/W
2
0
2
0
Product Specification
and
U0TENL
Table
R/W
R/W
1
0
1
0
37, form a 
SPIENL
R/W
R/W
0
0
0
0
57