Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 64

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
Caution:
System Exceptions
Interrupt Vectors and Priority
Interrupt Assertion
The Z8FMC16100 Series Flash MCU supports multiple system exceptions. System
exceptions are generated for the following events:
•
•
•
•
System exceptions, excluding the WDT interrupt, are non-maskable and therefore cannot
be disabled by the interrupt controller (setting IRQE to 0 has no effect).
When an interrupt request occurs, the corresponding bit in the Interrupt Request register is
set. This bit is automatically cleared when the eZ8 CPU vectors to the Interrupt Service
Routine (ISR). Writing a 0 to the corresponding bit in the Interrupt Request register also
clears the interrupt request.
If an interrupt is disabled, software polls the appropriate interrupt request register bit and
clear the bit directly. The following style of coding to clear bits in the Interrupt Request
registers is not recommended. All incoming interrupts that are received between execution
of the first LDX command and the last LDX command are lost.

The following code segment is an example of a poor coding style which results in lost
interrupt requests:
To avoid missing interrupts, Zilog
in the Interrupt Request 0 register:
The interrupt controller supports three levels of interrupt priority. Level 3 interrupts are
always higher priority than Level 2 interrupts. Level 2 interrupts are always higher pri-
ority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or
Level 3), priority is assigned as specified in
LDX r0, IRQ0
AND r0, MASK
Q0, r0
ANDX IRQ0, MASK
Illegal Instruction trap
Watchdog Timer interrupt
Watchdog Timer RC oscillator failure
Primary oscillator failure
®
recommends the following style of coding to clear bits
Table
Z8FMC16100 Series Flash MCU
29.
Product Specification
System Exceptions
52