Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 178

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
on the unique slave address or the General Call/STARTBYTE address. The
automatically when the I2CISTAT register is read.
If configured through the
addressing, the most significant 7 bits of the first byte of the transaction are compared
against the
addressing, the first byte of the transaction is compared against {
and the second byte is compared against
Arbitration Lost Interrupts
Arbitration Lost interrupts (
in MASTER mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA).
The I
automatically when the I2CISTAT register is read.
Stop/Restart Interrupts
A Stop/Restart event interrupt (
is in SLAVE mode and a
transaction. The
a
master is expected to follow. This bit is cleared automatically when the I2CISTAT
register is read. The STOP/RESTART interrupt only occurs on a selected (address match)
slave.
Not Acknowledge Interrupts
Not Acknowledge interrupts (
Not Acknowledge is received or sent by the I
not set in the I
clears by setting the
the I
the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to
data sent. The
register.
General Purpose Timer Interrupt from Baud Rate Generator
If the I
the I2CCTL register = 1, an interrupt is generated when the baud rate generator (BRG)
counts down to 1. The baud rate generator reloads and continues counting, providing a
periodic interrupt. None of the bits in the I2CISTAT register are set, allowing the BRG in
the I
disabled.
STOP
2
2
2
C controller waits until it is cleared before performing any action. In SLAVE mode,
C controller to be used as a general-purpose timer when the I
C controller switches to SLAVE mode when this instance occurs. This bit clears
2
C controller is disabled (
or
RESTART
SLA[6:0]
2
NCKI
C Control register. In MASTER mode, the Not Acknowledge interrupt
RSTR
START
condition. When a restart occurs, a new transaction by the same
bit clears in SLAVE mode when software reads the I2CISTAT
bit in the I2C State Register indicates whether the bit was set due to
bits of the Slave Address register. If configured for 10-bit slave
STOP
ARBLST
MODE[1:0]
or
NCKI
or
SPRS
STOP
IEN
RESTART
bit = 1 in I2CISTAT) occur in MASTER mode when a
bit = 1 in I2CISTAT) occur when the I
bit = 1 in I2CISTAT) occurs when the I
bit. When this interrupt occurs in MASTER mode,
bit in the I2CCTL register = 0) and the
SLA[7:0]
field of the I
condition is received, indicating the end of the
2
C controller and the
.
Z8FMC16100 Series Flash MCU
2
C Mode register for 7-bit slave
Product Specification
11110
START
,
SLA[9:8]
2
C controller is
2
C controller is
or
SAM
2
I
C controller
BIRQ
2
STOP
C Interrupts
bit clears
,R/W}
bit in
bit is
166