Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 109

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Z8FMC16100 Series Flash MCU
Product Specification
97
If TPOL is set to 1, the ratio of the PWM output High time to the total period is determined
by the equation:
PWM Value
PWM Output High Time Ratio (%) =
x 100
Reload Value
CAPTURE Modes
There are three capture modes that provide slightly different methods for recording the
time or time interval between, Timer Input events. These modes are CAPTURE mode,
CAPTURE RESTART mode, and CAPTURE COMPARE mode. In all three modes, when
the appropriate Timer Input transition (capture event) occurs, the timer counter value is
captured and stored in the PWM High and Low Byte registers. The
bit in the Timer
TPOL
Control 1 register determines whether the Capture occurs on a rising edge or a falling edge
of the Timer Input signal. The
bit determines whether interrupts are generated
TICONFIG
on capture events, reload events, or both. The
bit in Timer Control 0 register clears
INCAP
to indicate an interrupt caused by a reload event and sets to indicate the timer interrupt is
caused by an input capture event.
There is a delay from the input event to the timer capture of 2–3 system clock cycles, due
to internal synchronization logic.
If the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or High to Low) at timer reload. The initial value is determined by the
bit.
TPOL
In CAPTURE mode, and after it is enabled, the timer counts continu-
CAPTURE Mode—
ously and rolls over from
to
. When the capture event occurs, the timer
FFFFh
0000h
counter value is captured and stored in the PWM High and Low Byte registers, an inter-
rupt is generated, and the timer continues counting. The timer continues counting up to the
16-bit reload value stored in the Timer Reload High and Low Byte registers. Upon reach-
ing the reload value, the timer generates an interrupt and continues counting.
In CAPTURE RESTART mode, after it is enabled, the
CAPTURE RESTART Mode—
timer counts continuously until the capture event occurs or the timer count reaches the 16-
bit compare value stored in the Timer Reload High and Low Byte registers. If the capture
event occurs first, the timer counter value is captured and stored in the PWM High and
Low Byte registers. An interrupt is generated, the count value in the Timer High and Low
Byte registers is reset to
, and counting resumes. If no capture event occurs, upon
0001h
reaching the reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to
, and counting resumes.
0001h
CAPTURE/COMPARE Mode—
CAPTURE/COMPARE mode is identical to CAPTURE
RESTART mode, except that counting does not start until the first external Timer Input
transition occurs. Every subsequent transition (after the first) of the Timer Input signal
captures the current count value. When the capture event occurs, an interrupt is generated,
PS024613-0910
Timer Operating Modes