Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 277

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 145. Analog-to-Digital Converter Electrical Characteristics and Timing
Table 144. Reset and Stop Mode Recovery Pin Timing
PS024613-0910
Symbol Parameter
T
T
Symbol Parameter
DNL
INL
DNL
INL
V
RESET
SMR
REF
Resolution
Throughput conversion
ADCCLK frequency
Differential nonlinearity
for 8-bit use
Integral nonlinearity
for 8-bit use
Differential nonlinearity
for 10-bit
Integral nonlinearity
for 10-bit
Offset error
Gain error
On-chip voltage
reference
Analog input voltage
range
RESET pin assertion to
initiate a System Reset.
Stop Mode Recovery pin
pulse rejection period
Table 144
Mode Recovery functions.
Table 145
trates the input frequency response of the ADC.
provides electrical characteristics and timing information for the Reset and Stop
provides electrical characteristics and timing information for the ADC and illus-
Minimum Typical
–0.99
–1.25
Minimum
–25
–30
1.9
10
13
0
10
T
4
T
A
A
= –40 ºC to 105 ºC
= –40 ºC to 105 ºC
—
Typical
2
2
2
20
—
On-Chip Peripheral AC and DC Electrical Characteristics
Maximum
Maximum
V
1.25
1.25
2.1
20
30
25
REF
40
—
Z8FMC16100 Series Flash MCU
Units Conditions
Units Conditions
CLKs ADC clock cycles.
T
MHz
LSB
LSB
LSB
LSB
LSB
bits
mV
ns
CLK
V
V
RESET, DBG, and GPIO
Product Specification
Not in STOP mode.
T
period.
pins configured as SMR
sources.
External V
20 MHz sys clock with
ADC clock divided by 4
20 MHz sys clock with
ADC clock divided by 4
20 MHz sys clock with
ADC clock divided by 4
20 MHz sys clock with
ADC clock divided by 4
CLK
= System Clock
REF
= 2.0 V.
265