Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 82

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
PWM Duty Cycle Registers
Independent and Complementary PWM Outputs
Manual Off-State Control of PWM Output Channels
Deadband Insertion
The PWM Duty Cycle registers (PWMH0D, PWML0D, PWMH1D, PWML1D, PWMH2D,
and PWML2D) contain a 16-bit signed value, in which bit 15 is the sign bit. The Duty Cycle
value is compared to the current 12-bit unsigned PWM count value. If the PWM Duty Cycle
value is set less than or equal to 0, the PWM output is deasserted for the full PWM period. If
the PWM Duty Cycle value is set to a value greater than the PWM reload value, the PWM
output is asserted for the full PWM period.
The six PWM outputs are configured to operate independently or as three complementary
pairs. Operation as six independent PWM channels is enabled by setting the INDEN bit in
PWM Control 1 register (PWMCTL1). The
independent mode, each PWM output uses its own PWM duty cycle value.
When configured to operate as three complementary pairs, the PWM duty cycle values
PWMH0D, PWMH1D, and PWMH2D control the modulator output. In complementary
output mode, deadband time is also inserted.
The POLx bits in the PWM Control 1 register (PWMCTL1) select the relative polarity of
the High and Low signals. As displayed in
cleared to 0, the High PWM output will start in the ON state and transition to the OFF
state when the PWM timer count reaches the programmed duty cycle. The Low PWM
value starts in the OFF state and transitions to the ON state as the PWM timer count
reaches the value in the associated duty cycle register. Setting the POLx causes the High
output to start in the OFF state and the Low output to start in the ON state.
Each PWM output is controlled directly by the modulator logic or set to the OFF state. To
manually set the PWM outputs to the OFF state, set the
OUTx
individually by channel. For example, suppressing the single output of a pair allows the
complementary channel to continue operating. Similarly, if outputs are operating indepen-
dently, disabling one output channel has no effect on the other PWM outputs.
When PWM outputs are configured to operate as complementary pairs, an 8-bit deadband
value can be defined in the PWM Deadband register (PWMDB). Inserting deadband time
causes the modulator to separate the deassertion of one PWM signal from the assertion of
its complement. This separation is essential for many motor control applications in that it
prevents simultaneous turn-on of the High and Low drive transistors. The deadband counter
directly counts system clock cycles and is unaffected by PWM prescaler settings. The
bits in the PWM Output Control register (PWMOUT). OFF state control operates
Figure 8
PWEN
bit must be cleared to alter this bit. In
and
Z8FMC16100 Series Flash MCU
Figure
OUTCTL
9, when the POLx bits are
Product Specification
PWM Duty Cycle Registers
bit and the associated
70