Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 194

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 92. I
BITS
FIELD
RESET
R/W
ADDR
PS024613-0910
I
I
2
2
2
C Data Register
C Data Register (I2CDATA)
C Interrupt Status Register
7
11. The bus cycles through steps 7 to 10 until the final byte has been transferred. If the
12. The software responds to the
13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a
14. The slave I
15. The software responds to the
The I
register to transmit onto the I
the Shift register after it is received from the I
ble in the Register File address space, but is used only to buffer incoming and outgoing
data.
Writes by the software to the I2CDATA register are blocked if a slave Write transaction is
underway (the I
The read-only I
I
more of the TDRE, RDRF, SAM, ARBLST, SPRS or NCKI bits is set. The GCA and RD
bits do not generate an interrupt but rather provide status associated with the SAM bit
interrupt.
2
C interrupt and provides status of the I
software has not yet loaded the next data byte when the master brings SCL Low to
transfer the most significant data bit, the slave I
data register is written.
When a Not Acknowledge is received by the slave, the I
in the I2CISTAT register, causing the NAK interrupt to be generated.
register and by asserting the
STOP
I2CISTAT register).
clearing the
2
C Data register
or
6
RESTART
2
2
2
C controller asserts the
SPRS
C controller is in SLAVE mode, and data is being received).
C Interrupt Status register
(Table
bit.
condition on the bus.
5
92) contains the data that is to be loaded into the Shift 
2
C bus. This register also contains data that is loaded from
FLUSH
NAK
STOP
4
interrupt by clearing the
STOP/RESTART
DATA
F50H
interrupt by reading the I2CISTAT register and
R/W
bit of the I2CCTL register.
0
2
C controller
(Table
2
C bus. The I
3
2
93) indicates the cause of any current
C controller holds SCL Low until the
Z8FMC16100 Series Flash MCU
.
interrupt (sets the
When an interrupt occurs, one or
2
2
2
C Shift register is not accessi-
C controller sets the
TXI
Product Specification
bit in the I2CCTL
1
SPRS
I
2
C Data Register
NCKI
bit in the
0
bit
182