Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 129

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
1
0
Idle State
of Line
Figure 15. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format
The character format is given below.
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the
MULTIPROCESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide
MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the LIN-UART Address Compare register holds the network
address of the device.
MULTIPROCESSOR Mode Receive Interrupts
When MULTIPROCESSOR (9-bit) mode is enabled, the LIN-UART processes only frames
addressed to it. The determination of whether a frame of data is addressed to the LIN-UART
can be made in hardware, software or a combination of the two, depending on the
multiprocessor configuration bits. In general, the address compare feature reduces the load
on the CPU, as it does not need to access the LIN-UART when it receives data directed to
other devices on the multinode network. The following 3 MULTIPROCESSOR modes are
available in hardware:
1. Interrupt on all address bytes
2. Interrupt on matched address bytes and correctly framed data bytes
3. Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the LIN-UART Control 1 register. For all
MULTIPROCESSOR modes, bit MPEN of the LIN-UART Control 1 register must be set
to 1.
The first scheme is enabled by writing
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine checks the address byte which triggered the interrupt. If it matches the
LIN-UART address, the software clears MPMD[0]. At this point, each new incoming byte
interrupts the CPU. The software determines the end of the frame and checks for it by
reading the MPRX bit of the LIN-UART Status 1 register for each incoming byte. If
MPRX=1
LIN-UART’s address, then MPMD[0] must be set to 1 by software, causing the LIN-
Start
Bit 0
, a new frame has begun. If the address of this new frame is different from the
lsb
Bit 1
Bit 2
Bit 3
Data Field
Bit 4
01b
to MPMD[1:0]. In this mode, all incoming
Bit 5
Bit 6
Z8FMC16100 Series Flash MCU
Bit 7
msb
Product Specification
MULTIPROCESSOR Mode
MP
Stop Bit(s)
1
2
117