Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 134

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
Note:
LIN-UART Interrupts
received or software forces a state change. When it is in Active State (autobaud has
completed), a Break of 10 or more bit times is recognized and will cause a transition to the
Autobaud state.
If the Identifier character indicates that this slave device is not participating in the
message, software can set the
rest of the message. No further receive interrupts will occur until the next Break.
The LIN-UART features separate interrupts for the transmitter and receiver. In addition,
when the LIN-UART primary functionality is disabled, the BRG can also function as a
basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data register Empty bit
(
transmission. The TDRE interrupt occurs when the transmitter is initially enabled and
after the Transmit shift register has shifted the first bit of a character out. At this point, the
Transmit Data register may be written with the next character to send. This provides 7 bit
periods of latency to load the Transmit Data register before the Transmit shift register
completes shifting the current character. Writing to the LIN-UART Transmit Data register
clears the
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
In MULTIPROCESSOR mode (
the multiprocessor configuration and the most recent address byte.
•
•
•
•
TDRE
A data byte is received and is available in the LIN-UART Receive Data register. This
interrupt can be disabled independent of the other receiver interrupt sources through the
RDAIRQ
interrupt occurs after the receive character is placed in the Receive Data register.
Software must respond to this received data available condition before the next
character is completely received to avoid an overrun error.
A break is received.
A receive data overrun or LIN slave autobaud overrun error is detected.
A data framing error is detected.
A parity error is detected (physical layer error in LIN mode).
) is set to 1. This indicates that the transmitter is ready to accept new data for
TDRE
bit (this feature is useful in devices which support DMA). The received data
bit to 0.
LinState[1:0]
MPEN
=
1
), the receive data interrupts are dependent on
=
01b
Z8FMC16100 Series Flash MCU
(Wait for Break State) to ignore the
Product Specification
LIN-UART Interrupts
122