Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 188

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
register). The I
the value in the
General Call and Start Byte Address Recognition—
address phase, and the controller is configured for MASTER/SLAVE or SLAVE in either
7- or 10-bit address modes, the hardware detects a match to the General Call Address or
the START byte and generates the slave address match interrupt. A General Call Address
is a 7-bit address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all 0’s
with the R/W bit = 1. The
the I2CISTAT register distinguishes a General Call Address from a START byte which is
cleared to 0 for a General Call Address).
For a General Call Address, the I
acknowledge phase with the value in the
set to process the data bytes associated with the
following the
before deciding to set or clear the
A START byte will not be acknowledged—a requirement of the I
Software Address Recognition—
must be set to 1 prior to the reception of the address byte(s). When
byte generates a receive interrupt (
examine each byte and determine whether to set or clear the
Low during the Acknowledge phase until the software responds by writing to the I2CCTL
register. The value written to the
releasing the SCL. The
phase, but the
Slave Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate data transferred from
the master to the slave, and the unshaded regions indicate the data transferred from the
slave to the master. The transaction field labels are defined as follows:
S
W
A
A
P
Start
Write
Acknowledge
Not Acknowledge
Stop
RD
SAM
2
NAK
C controller automatically responds during the Acknowledge phase with
bit is updated based on the first address byte.
interrupt to allow the software to examine each received data byte
bit of the I2CCTL register.
SAM
SAM
and
and
NAK
2
NAK
C controller automatically responds during the address
RDRF
GCA
GCA
To disable hardware address recognition, the
bit is used by the controller to drive the I
bit.
bits are not set when
bits are set in the I2CISTAT register. The
= 1 in the I2CISTAT register). The software must
NAK
bit of the I2CCTL register. If the software is
GCA
Z8FMC16100 Series Flash MCU
bit, the
If
GCE
NAK
IRM
IRM
= 1 and
Product Specification
bit. The slave holds SCL
2
bit can optionally be set
C specification.
= 1 during the address
IRM
IRM
= 1, each received
Slave Transactions
= 0 during the
2
C bus, then
RD
IRM
bit in
bit
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