Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 15

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
CPU and Peripheral Overview
Pulse Width Modulator for Motor Control Applications
10-Bit Analog-to-Digital Converter
Zilog’s latest 8-bit eZ8 CPU meets the continuing demand for faster and more code-
efficient microcontrollers. The eZ8 CPU executes a superset of original Z8
set. The eZ8 CPU features include:
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For more details on the eZ8 CPU, refer to eZ8 CPU User Manual (UM0128), available for
download at www.zilog.com.
To rotate a 3-phase motor three voltage and current signals must be supplied, each 120°
shifted from each other. To control a 3-phase motor, the MCU must provide 6 PWM
outputs. The Z8FMC16100 Series Flash MCU features a flexible PWM module with three
complementary pairs or six independent PWM outputs supporting deadband operation and
fault protection trip input. These features provide multiphase control capability for various
motor types and ensure safe operation of the motor by providing immediate shutdown of
the PWM pins during fault condition.
The Z8FMC16100 Series Flash MCU devices feature up to eight channels of 10-bit analog-
to-digital conversion.
Direct register-to-register architecture allows each register to function as an
Software stack allows much greater depth in subroutine calls and interrupts than
Compatible with existing Z8 assembly code
New instructions improve execution efficiency for code developed using higher-level
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2-9 clock cycles per instruction
accumulator, improving execution time, and decreasing the required program memory
hardware stacks
programming languages, including ‘C’ language
LDCI, LEA, MULT, and SRL
Z8FMC16100 Series Flash MCU
CPU and Peripheral Overview
Product Specification
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