Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 34

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 7. System Reset Sources and Resulting Reset Action
PS024613-0910
Operating Mode System Reset Source
NORMAL or
HALT modes
STOP mode
System Reset
Note:
During a system reset, the Z8FMC16100 Series Flash MCU is held in RESET for
66 cycles of internal precision oscillator (IPO). At the beginning of RESET, all GPIO pins
are configured as inputs. All GPIO programmable pull-ups are disabled.
At the beginning of a System Reset, the motor control PWM outputs are forced to high-
impedance momentarily. When the Option Bits which control the off-state have been
properly evaluated the PWM outputs are forced to the programmed off-state.
During RESET, the eZ8 CPU and on-chip peripherals are idle; however, the IPO and
WDT oscillator continue to run. During the first 50 clock cycles the internal option bit
registers are initialized after which the system clock for the core and peripherals begins
operating. The eZ8 CPU and on-chip peripherals remain idle through the next 16 cycles of
the system clock after which time the internal reset signal is deasserted.
On RESET, control registers within the Register File which have a defined reset value are
loaded with their reset values. Other control registers (including the Flags) and general-
purpose RAM are undefined following RESET. The eZ8 CPU fetches the RESET vector
at Program Memory addresses
Counter. Program execution begins at the RESET vector address.
Table 7
following provides more detailed information on the individual RESET sources.
A POR/VBO event always has priority over all other possible reset sources to ensure a full
system reset occurs.
POR/VBO.
WDT timeout when configured for reset. System Reset.
RESET pin assertion.
Write OCDCTL[0] to 1.
Fault detect logic reset.
Power-on reset/Voltage Brownout.
RESET pin assertion.
Fault detect logic reset.
lists the system reset sources as a function of the operating mode. The text
0002h
and
0003h
Action
System Reset.
System Reset except the OCD is not reset.
System Reset.
System Reset.
System Reset.
System Reset.
System Reset.
and loads that value into the Program
Z8FMC16100 Series Flash MCU
Product Specification
System Reset
22