Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 167

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 84. SPI Data Register (SPIDATA)
Table 85. SPI Control Register (SPICTL)
PS024613-0910
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
SPI Data Register
SPI Control Register
IRQE
7
7
The SPI Data register stores both the outgoing (transmit) data and the incoming (receive)
data. Reads from the SPI Data register always return the current contents of the 8-bit shift
register. Data is shifted out starting with bit 7. The last bit received resides in bit position 0.
With the SPI configured as a master, writing a data byte to this register initiates data
transmission. With the SPI configured as a slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external master. In either
MASTER or SLAVE mode, if a transmission is already in progress, Writes to this register
are ignored and the overrun error flag, OVR, is set in the SPI Status register.
When character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode
register), the transmit character must be left-justified in the SPI Data register. A received
character of less than 8 bits is right-justified (the final bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be written
to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0], see
DATA—Data
Transmit and/or receive data.
The SPI Control register configures the SPI for transmit and receive operations.
STR
6
6
BIRQ
5
5
PHASE
4
4
DATA
F60H
F61H
R/W
R/W
00H
X
CLKPOL
3
3
Z8FMC16100 Series Flash MCU
WOR
2
2
Product Specification
MMEN
1
1
SPI Data Register
Table
SPIEN
0
0
84.
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