Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 170

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 87. SPI Mode Register (SPIMODE)
PS024613-0910
BITS
FIELD
RESET
R/W
ADDR
Caution:
SPI Mode Register
7
SLAS—Slave Select
If SPI enabled as a Slave,
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
The SPI Mode register configures the character bit width and the direction and value of the
SS pin.
Reserved—Must be 0.
DIAG—Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPI-
BRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and
Low byte values are not buffered.
Exercise caution if reading the values while the BRG is counting.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. Refer to the SPI
Data register description for information on valid bit positions when the character length is
less than 8-bits.
Reserved
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
R
6
DIAG
5
4
F63H
00H
NUMBITS[2:0]
3
R/W
Z8FMC16100 Series Flash MCU
2
Product Specification
SSIO
1
SPI Mode Register
SSV
0
158