Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 127

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
Clear To Send Operation
External Driver Enable
The LIN-UART is now configured for interrupt-driven data reception. When the LIN-
UART Receiver interrupt is detected, the associated ISR performs the following:
1. Check the LIN-UART Status 0 register to determine the source of the interrupt-error,
2. If the interrupt was due to data available, read the data from the LIN-UART Receive
3. Execute the IRET instruction to return from the interrupt-service routine and await
The Clear To Send (CTS) pin, if enabled by the
register, performs flow control on the outgoing transmit data stream. The Clear To Send
(CTS) input pin is sampled one system clock before beginning any new character
transmission. To delay transmission of the next data character, an external receiver must
deassert CTS at least one system clock cycle before a new data transmission begins. For
multiple character transmissions, this operation is typically performed during the Stop Bit
transmission. If CTS deasserts in the middle of a character transmission, the current
character is sent completely.
The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multitransceiver bus, such as RS-485.
Driver Enable is a programmable polarity signal that envelopes the entire transmitted data
frame including parity and Stop bits as displayed in
asserts when a byte is written to the LIN-UART Transmit Data register. The Driver Enable
signal asserts at least one bit period and no greater than two bit periods before the Start bit
is transmitted. This allows a setup time to enable the transceiver.
The Driver Enable signal deasserts one system clock period after the last
transmitted. This one system clock delay allows both time for data to clear the transceiver
before disabling it, as well as the ability to determine if another character follows the
current character. In the event of back to back characters (new data must be written to the
Transmit Data register before the previous character is completely transmitted) the DE
signal is not deasserted between characters. The
register 1 sets the polarity of the Driver Enable signal.
break, or received data.
Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the multiprocessor mode bits
more data.
CTSE
DEPOL
Z8FMC16100 Series Flash MCU
Figure
bit of the LIN-UART Control 0
bit in the LIN-UART Control
MPMD
14. The Driver Enable signal
Product Specification
[1:0].
Clear To Send Operation
Stop
bit is
115