Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 132

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
software. In the LIN Slave mode, the
moves through the Wait For Break, AutoBaud, and Active states.
The Noise Filter may also need to be enabled and configured when interfacing to a LIN
bus.
LIN MASTER Mode Operation
LIN MASTER mode is selected by setting
=
LinState
The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the
Control register. The transmission of the Break is performed by setting the
Control 0 register. The LIN-UART starts the Break once the
character transmission currently underway has completed. The
hardware once the break is completed.
The Synch character is transmitted by writing a
must = 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.
The Identifier character is transmitted by writing the appropriate value to the Transmit
Data register (
If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data register when the
transmit data register is written after
inserts one or two stop bits between each character as determined by the
Control0 register. Additional idle time occurs between characters if
next character is written.
If the selected slave is sending the response portion of the frame to the master, each receive
byte is signalled by the receive data interrupt (
If the selected slave is sending the response to a different slave, the master can ignore the
response characters by deasserting the
slot has completed.
LIN Sleep Mode
While the LIN bus is in the sleep state, the CPU can be in either low power STOP mode, in
HALT mode, or in normal operational state. Any device on the LIN bus may issue a Wake-
up message if it requires the master to initiate a LIN message frame. Following the Wake-
up message, the master wakes up and initiates a new message. A Wake-up message is
accomplished by pulling the bus low for at least 250 µs but less than 5 ms. Transmitting a
00h
11B.
character is one way to transmit the wake-up message.
If the LIN bus protocol indicates the bus is required go into the LIN sleep state, the
[1:0] bits must be set =
TDRE
must = 1 before writing).
00B
LinState
TDRE
REN
by software.
LMST
bit in the Control0 register until the frame time
asserts, but before
RDA
= 1,
55H
field is updated by hardware as the Slave
bit is set in the Status0 register).
Z8FMC16100 Series Flash MCU
LSLV
to the Transmit Data register (
TxBreakLength
= 0,
TXE
ABEN
Product Specification
SBRK
SBRK
TDRE
TXE
asserts, the hardware
= 0,
bit is deasserted by
bit is set and any
bit asserts. If the
asserts before the
LIN Protocol Mode
LinState
field of the LIN
Stop
SBRK
bit in the
bit in the
TDRE
[1:0]
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