Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 185

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
S
Slave Address
1st Byte
Figure 31. Data Transfer Format—Master Read Transaction with a 10-Bit Address
5. The I
6. The I
7. The I
8. The I
9. The I
10. The software responds by reading the I
11. The I
12. If there are more bytes to transfer, the I
13. A NAK interrupt (
14. The software responds by setting the STOP bit of the I
15. A
Master Read Transaction with a 10-Bit Address
Figure 31
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:
1. The software initializes the
next High period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends a
is complete, and the following steps can be ignored.
the final byte, the software must set the
final byte; otherwise, it sends an Acknowledge.
mode with 7- or 10-bit addressing (the I
address types). The
W=0 A Slave Address
STOP
2
2
2
2
2
2
displays the read transaction format for a 10-bit addressed slave.
C controller sends a
C controller sends the address and Read bit out via the SDA signal.
C slave acknowledges the address by pulling the SDA signal Low during the
C controller shifts in the first byte of data from the I
C controller asserts the receive interrupt.
C controller sends a Not Acknowledge to the I
STOP
condition is sent to the I
2
C Status register, sets the
condition on the bus, and clears the
2nd Byte
NCKI
TXI
MODE
bit. The I
bit in I2CISTAT) is generated by the I
field selects the address width for this mode when addressed
START
A S Slave Address
MODE
2
field in the I
C slave.
2
condition.
C controller flushes the Transmit Data register,
ACKV
1st Byte
2
2
C Data register. If the next data byte is to be
NAK
2
C controller returns to Step 7.
C bus protocol allows the mixing of slave
bit, and clears the
bit of the I
2
C Mode register for MASTER/SLAVE
11110XX
Z8FMC16100 Series Flash MCU
STOP
R=1
2
C slave if the next byte is the
2
and
2
C Control register.
C Control register.
2
. The two
A
C controller sets the NCKI
2
C slave on the SDA signal.
NCKI
Product Specification
Data
ACK
2
C controller.
bits. The transaction
bit in the I
XX
Master Transactions
A
bits are the two
Data
2
C State
STOP
A P
173