Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 253

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
OCD Data Format
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Entering DEBUG Mode
The device enters DEBUG mode following any of the below operations:
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Exiting DEBUG Mode
The device exits DEBUG mode following any of the below operations:
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The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 start bit, 8 data bits (least-significant bit first), and 1 stop bit, see
Figure
ST = Start Bit
SP = Stop Bit
D0—D7 = Data Bits
The system clock operates unless in STOP mode
All enabled on-chip peripherals operate unless in STOP mode or otherwise defined by
the on-chip peripheral to disable in DEBUG mode
Automatically exits HALT mode
Constantly refreshes the Watchdog Timer (if enabled)
Writing the DBGMODE bit in the OCD Control register to 1 using the OCD interface
eZ8 CPU execution of a BRK (break point) instruction (when enabled)
Match of PC to OCDCNTR register (when enabled)
OCDCNTR register decrements to
The DBG pin is Low when the device exits Reset
Clearing the DBGMODE bit in the OCD Control register to 0
Power-On reset
Voltage Brownout reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in STOP mode initiates a System Reset
44.
ST
D0
D1
Figure 44. OCD Data Format
D2
0000h
D3
(when enabled)
D4
Z8FMC16100 Series Flash MCU
D5
Product Specification
D6
OCD Data Format
D7
SP
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