Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 243

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 129. Oscillator Control Register (OSCCTL)
BITS
FIELD
RESET
R/W
ADDR
* The reset value is 1 if the option bit LPDEN is 0.
PS024613-0910
Clock Failure Detection and Recovery for WDT Oscillator
Oscillator Control Register
INTEN
R/W
7
1
the Watchdog Timer (WDT) oscillator to drive the system clock. Although this oscillator
runs at a much lower frequency than the original system clock, the CPU continues to oper-
ate, allowing execution of a clock failure vector and software routines that either remedy
the oscillator failure or issue a failure alert. This automatic switch-over is not available if
the WDT is the primary oscillator.
If the system clock frequency drops below 1 kHz ±50%, the primary oscillator failure
detection circuitry asserts. For operating frequencies below 2 kHz, do not enable the clock
failure circuitry (
In the event of a WDT oscillator failure, a System Exception is issued if the
the OSCCTL register is set. This event does not trigger an attendant clock switch-over, but
alerts the CPU of the failure. After a WDT failure, it is no longer possible to detect a pri-
mary oscillator failure.
The WDT oscillator failure detection circuit counts system clocks while looking for a
WDT clock. The logic counts 8000 system clock cycles before determining that a failure
occurred. The system clock rate determines the speed at which the WDT failure can be
detected. A very slow system clock results in very slow detection times. If the WDT is the
primary oscillator or if the Watchdog Timer oscillator is disabled, deassert the
of the OSCCTL register.
The Oscillator Control register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry, actively powers down the flash,
and selects the primary oscillator, which becomes the system clock.
The Oscillator Control register must be unlocked before writing. Writing the two-step
sequence
register locks after completion of a register write to the OSCCTL.
XTLEN
R/W
E7H
6
0
followed by
POFEN
WDTEN
R/W
5
1
must be deasserted in the OSCCTL register).
18H
POFEN
to the Oscillator Control register address unlocks it. The
R/W
4
0
Clock Failure Detection and Recovery for WDT Oscillator
F86H
WDFEN
R/W
3
0
Z8FMC16100 Series Flash MCU
FLPEN
R/W
0*
2
Product Specification
1
SCKSEL
R/W
WDFEN
00
WDFEN
0
bit of
bit
231