Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 107

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

PS024613-0910
Follow the steps below to configure a timer for COUNTER and COMPARATOR
COUNTER modes and initiate the count:
1. Write to the Timer Control registers to:
2. Write to the Timer High and Low Byte registers to set the starting count value. This
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
5. Configure the associated GPIO port pin for the Timer Input alternate function
6. If using the Timer Output function, configure the associated GPIO port pin for the
7. Write to the Timer Control 1 register to enable the timer.
PWM SINGLE and DUAL OUTPUT Modes
In PWM SINGLE OUTPUT mode, the timer outputs a PWM output signal through a
GPIO port pin. In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal
and also its complement through two GPIO port pins. The timer first counts up to the
16-bit PWM match value stored in the Timer PWM High and Low Byte registers. When
the timer count value matches the PWM value, the Timer Output toggles. The timer con-
tinues counting until it reaches the reload value stored in the Timer Reload High and Low
Byte registers. On reaching the reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to
The Timer Output signal begins with a value equal to
the timer value matches the PWM value. The Timer Output signal returns to
the timer reaches the reload value and is reset to
In PWM DUAL OUTPUT mode, the timer also generates a second PWM output signal,
Timer Output Complement (T
field) to delay (0–128 system clock cycles) the Low to a High (inactive to active) output
transitions on these two pins. This configuration ensures a time gap between the deassertion
of one PWM output to the assertion of its complement.
(a) Disable the timer.
(b) Configure the timer for COUNTER or COMPARATOR COUNTER mode.
(c) Select either the rising edge or falling edge of the Timer Input or comparator
setting only affects the first pass in the counter modes. After the first timer reload,
counting begins at the reset value of
to the relevant interrupt registers.
(COUNTER mode).
Timer Output alternate function.
output signal for the count. This choice also sets the initial logic level (High or
Low) for the Timer Output alternate function. However, the Timer Output
function does not have to be enabled.
OUT
). A programmable deadband can be configured (
0001h
.
0001h
Z8FMC16100 Series Flash MCU
TPOL
.
0001h
and then transits to
Product Specification
, and counting resumes.
Timer Operating Modes
TPOL
TPOL
PWMD
when
after
95