Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 196

• Manufacturer Part Number: Z8FMC160100KITG
• Description: KIT DEV FOR Z8 ENCORE Z8FMC16100
• Manufacturer: Zilog
• Series: Z8 Encore! MC™r

Specifications of Z8FMC160100KITG

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: Z8FMC16100
• Primary Attributes: 3-Ph DC Motors
• Secondary Attributes: Graphical User Interface
• For Use With: 269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4660

Table 94. I
BITS
FIELD
RESET
R/W
ADDR
PS024613-0910
Note:
I
2
2
C Control Register
C Control Register (I2CCTL)
R/W
IEN
7
0
SPRS—Stop/Restart Condition Interrupt
This bit is set when the I
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT register is read. Read the
whether the interrupt was caused by a STOP or RESTART condition.
NCKI—NAK Interrupt
In Master mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the
by setting the
In Slave mode, this bit is set when a Not Acknowledge condition is received (Master read-
ing data from Slave), indicating the Master is finished reading. A STOP or RESTART con-
dition follows. In Slave mode this bit clears when the I2CISTAT register is read.
The I
R/W1 - bit may be set (write 1) but not cleared.
IEN—I
This bit enables the I
START—Send Start Condition
When set, this bit causes the I
Start condition. Once asserted, it is cleared by the I
condition or by deasserting the
the bit. After this bit is set, the START condition is sent if there is data in the I2CDATA or
I2CSHIFT register. If there is no data in one of these registers, the I
until data is loaded. If this bit is set while the I
ates a RESTART condition after the byte shifts and the acknowledge phase completes. If
the
condition.
If START is set while a slave mode transaction is underway to this device, the START bit
will be cleared and ARBLST bit in the Interrupt Status register will be set.
STOP
2
C Control register
2
START
C Enable
R/W1
bit is also set, it also waits until the STOP condition is sent before the START
START
6
0
START
nor the
STOP
2
R/W1
or
C Controller.
5
0
STOP
(Table
2
C Controller is enabled in Slave mode and detects a STOP or
STOP
bits. 
2
C Controller (when configured as the Master) to send the
94) enables and configures I
IEN
bit is active. In Master mode, this bit can only be cleared
BIRQ
R/W
4
0
bit. If this bit is 1, it cannot be cleared by writing to
RSTR
F52H
bit of the I2CSTATE register to determine
R/W
TXI
2
3
0
C Controller is shifting out data, it gener-
2
Z8FMC16100 Series Flash MCU
C Controller after it sends the Start
R/W1
NAK
2
0
2
C operation.
Product Specification
FLUSH
2
R/W
C Controller waits
1
0
I
2
C Control Register
FILTEN
R/W
0
0
184