UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 241
UPD78F1144AGB-GAH-AX
Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
1 000
Company:
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
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Remark
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAU stop
Figure 6-54. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
n = 0 to 7, k = 0 to 6
Sets the TAU0EN bit of the PER0 register to 1.
Sets the TPS0 register.
Sets the TMR0n register (determines operation mode of
channel).
Clears TOE0k to 0 and stops operation of TO0k.
Sets the TS0n bit to 1.
Detects TI0k pin input count start valid edge.
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TMR0n register, TOM0n, TOL0n, TO0n,
and TOE0n bits cannot be changed.
The TT0n bit is set to 1.
The TAU0EN bit of PER0 register is cleared to 0.
Determines clock frequencies of CK00 and CK01.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TT0n bit automatically returns to 0 because it is a
trigger bit.
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
TE0n = 1, and the TI0k pin start edge detection wait
status is set.
Clears TCR0n to 0000H and starts counting up.
When the TI0k pin start edge is detected, the counter
(TCRn) counts up from 0000H. If a capture edge of the
TI0k pin is detected, the count value is transferred to
TDR0n and INTTM0n is generated.
If an overflow occurs at this time, the OVF bit of the
TSR0n register is set; if an overflow does not occur, the
OVF bit is cleared. TCR0n stops the count operation until
the next TI0k pin start edge is detected.
TE0n = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
TCR0n holds count value and stops.
The OVF bit of the TSR0n register is also held.
All circuits are initialized and SFR of each channel is
also initialized.
Hardware Status
239
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