UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 512

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.17 Communication operations
510
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
(2) Master operation in multimaster system
(3) Slave operation
The flowchart when using the 78K0R/KE3 as the master in a single master system is shown below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial
settings at startup. If communication with the slave is required, prepare the communication and then execute
communication processing.
In the I
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the 78K0R/KE3 takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the 78K0R/KE3 looses in arbitration and is specified as the slave is omitted here, and
only the processing as the master is shown.
communication. Then, wait for the communication request as the master or wait for the specification as the
slave.
transmission/reception with the slave and the arbitration with other masters.
An example of when the 78K0R/KE3 is used as the I
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait
for the INTIIC0 interrupt occurrence (communication waiting).
communication status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
2
C bus multimaster system, whether the bus is released or used cannot be judged by the I
The actual communication is performed in the communication processing, and it supports the
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
Execute the initial settings at startup to take part in a
2
C bus slave is shown below.
When an INTIIC0 interrupt occurs, the
2
C bus