UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 433

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(1) Register setting
SMRmn
SOE0
SOE1
SO0
SO1
SS0
SS1
Caution For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel n.
Remark
(a) Serial output register m (SOm) …The register that not used in this mode.
(b) Serial output enable register m (SOEm) …The register that not used in this mode.
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
(d) Serial mode register mn (SMRmn)
CKSmn
0/1
15
15
15
15
15
15
15
0
0
0
0
0
0
Figure 11-79. Example of Contents of Registers for UART Reception of UART
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 13
r: Channel number (r = n − 1),
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
CCSmn
14
14
14
14
14
14
14
0
0
0
0
0
0
0
: Setting is fixed in the UART reception mode,
13
13
13
13
13
13
13
0
0
0
0
0
0
0
12
12
12
12
12
12
12
0
0
0
0
0
0
0
11
11
11
11
11
11
11
0: Forward (normal) reception
1: Reverse reception
0
1
1
0
0
0
0
CHAPTER 11 SERIAL ARRAY UNIT
CKO02
(UART0, UART1, UART3) (1/2)
10
10
10
10
10
10
10
×
1
0
0
0
0
0
User’s Manual U17854EJ9V0UD
9
1
9
1
0
0
0
0
9
0
9
9
9
9
STSmn
CKO00
8
×
8
1
0
0
8
1
8
8
8
0
8
0
0
0
7
0
7
7
7
0
7
0
7
0
7
0
SISmn0
0/1
0
0
6
6
6
0
6
0
6
0
6
0
6
: Setting disabled (set to the initial value)
0
0
1
5
5
5
0
5
0
0
0
5
5
5
4
0
4
0
0
0
0
0
4
0
4
4
4
4
Interrupt sources of channel n
0: Transfer end interrupt
SS03
SS13
0/1
0/1
3
1
3
1
0
0
3
0
3
3
3
3
MDmn2
SOE02
SOE12
SO02
SO12
SS02
SS12
×
×
2
0
2
2
2
×
2
×
2
×
2
×
MDmn1
SS01
0/1
1
1
1
1
1
1
0
1
0
1
1
0
1
MDmn0
SOE00
SO00
SS00
×
1
0
0
0
0
×
0
0
0
×
0
0
0
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