UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 490

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

488
(5) IIC clock select register 0 (IICCL0)
Address: FFF54H
Symbol
IICCL0
This register is used to set the transfer clock for the I
IICCL0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are
read-only. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion
register 0 (IICX0) (see 12.5.4 Transfer clock setting method).
Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation clears this register to 00H.
Note Bits 4 and 5 are read-only.
Remark
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0).
The digital filter is used for noise elimination in fast mode.
Condition for clearing (CLD0 = 0)
• When the SCL0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
Condition for clearing (DAD0 = 0)
• When the SDA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
SMC0
DAD0
DFC0
CLD0
7
0
0
1
0
1
0
1
0
1
After reset: 00H
IICE0: Bit 7 of IIC control register 0 (IICC0)
Figure 12-9. Format of IIC Clock Select Register 0 (IICCL0)
The SCL0 pin was detected at low level.
The SCL0 pin was detected at high level.
The SDA0 pin was detected at low level.
The SDA0 pin was detected at high level.
Operates in standard mode.
Operates in fast mode.
Digital filter off.
Digital filter on.
6
0
CHAPTER 12 SERIAL INTERFACE IIC0
CLD0
Detection of SCL0 pin level (valid only when IICE0 = 1)
Detection of SDA0 pin level (valid only when IICE0 = 1)
<5>
R/W
User’s Manual U17854EJ9V0UD
Note
DAD0
<4>
Digital filter operation control
Operation mode switching
2
C bus.
Condition for setting (CLD0 = 1)
• When the SCL0 pin is at high level
Condition for setting (DAD0 = 1)
• When the SDA0 pin is at high level
SMC0
<3>
DFC0
<2>
CL01
1
CL00
0