UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 497

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.5 Acknowledge (ACK)
side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been
detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0).
slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops
transmission. If ACK is not returned, the possible causes are as follows.
of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 to 1
for reception (TRC0 = 0).
slave must inform the master, by clearing ACKE0 to 0, that it will not receive any more data.
ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any
more data (transmission will be stopped).
IICX0
CLX0
Bit 0
Caution Determine the transfer clock frequency of I
Remarks 1. ×:
ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a
<1> Reception was not performed normally.
<2> The final data item was received.
<3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0)
If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the
When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that
0
0
0
0
0
0
0
1
1
1
1
SMC0
Bit 3
0
0
0
0
1
1
1
0
1
1
1
2. f
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
CLK
IICCL0
CL01
Bit 1
: CPU/peripheral hardware clock frequency
0
0
1
1
0
1
1
×
0
1
1
don’t care
CL00
Bit 0
0
1
0
1
×
0
1
×
×
0
1
f
f
f
f
f
f
f
Setting prohibited
f
Setting prohibited
f
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Transfer Clock (f
CHAPTER 12 SERIAL INTERFACE IIC0
Table 12-3. Selection Clock Setting
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User’s Manual U17854EJ9V0UD
CLK
/m)
4.00 MHz to 8.4 MHz
8.38 MHz to 16.76 MHz
16.76 MHz to 20 MHz
2.00 MHz to 4.2 MHz
7.60 MHz to 16.76 MHz
16.00 MHz to 20 MHz
4.00 MHz to 8.4 MHz
8.00 MHz to 8.38 MHz
16.00 MHz to 16.76 MHz
4.00 MHz to 4.19 MHz
Settable Selection Clock
2
C by using CLX0, SMC0, CL01, and CL00 before
(f
CLK
) Range
Normal mode (SMC0 bit = 0)
Fast mode (SMC0 bit = 1)
Fast mode (SMC0 bit = 1)
Operation Mode
495