UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 625

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.1 Register for Confirming Reset Source
store which source has generated the reset request.
Many internal reset generation sources exist in the 78K0R/KE3. The reset control flag register (RESF) is used to
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
Notes 1.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 18-3.
Address: FFFA8H
Flag
TRAP
WDRF
LVIRF
Symbol
RESF
2.
2. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF flag may
The value after reset varies depending on the reset source.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Reset Source
become 1 from the beginning depending on the power-on waveform.
WDRF
LVIRF
TRAP
TRAP
7
0
1
0
1
0
1
After reset: 00H
Table 18-3. RESF Status When Reset Request Is Generated
Figure 18-5. Format of Reset Control Flag Register (RESF)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Cleared (0)
RESET Input
6
0
Note 1
CHAPTER 18 RESET FUNCTION
R
Internal reset request by execution of illegal instruction
Cleared (0)
User’s Manual U17854EJ9V0UD
Reset by POC
5
0
Internal reset request by low-voltage detector (LVI)
Internal reset request by watchdog timer (WDT)
WDRF
4
Set (1)
Held
Held
Reset by Execution
of Illegal Instruction
3
0
2
0
Set (1)
Held
Held
Reset by WDT
Note 2
1
0
Held
Held
Set (1)
Reset by LVI
LVIRF
0
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