UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 543

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UPD78F1144AGB-GAH-AX

Manufacturer Part Number
UPD78F1144AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1144AGB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
UPD78F1144AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2) Data
Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission.
WREL0
INTIIC0
WREL0
INTIIC0
ACKD0
MSTS0
ACKD0
MSTS0
ACKE0
ACKE0
Processing by master device
WTIM0
WTIM0
Transfer lines
Processing by slave device
SPD0
TRC0
SDA0
SPD0
TRC0
STD0
SPT0
SCL0
STD0
SPT0
STT0
STT0
IIC0
IIC0
2. To cancel a slave wait state, write “FFH” to IIC0 or set WREL0.
D0
8
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
ACK
Transmitting
9
Receiving
(When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
Figure 12-28. Example of Master to Slave Communication
IIC0
IIC0
D7
Note 2
1
data Note 1
CHAPTER 12 SERIAL INTERFACE IIC0
D6
FFH Note 2
2
D5
3
User’s Manual U17854EJ9V0UD
D4
4
D3
5
D2
6
D1
7
D0
8
ACK
9
IIC0
IIC0
data Note 1
D7
Note 2
1
D6
FFH Note 2
2
D5
3
541

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