UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 56

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Option byte area
(4) On-chip debug security ID setting area
54
(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT).
Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2
bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to
010C3H when the boot swap is used. For details, see CHAPTER 22 OPTION BYTE.
A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID
setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not
used and at 000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see
CHAPTER 24 ON-CHIP DEBUG FUNCTION.
Vector Table Address
0000CH
0001CH
0000AH
0000EH
0001AH
0001EH
00000H
00004H
00006H
00008H
00010H
00012H
00014H
00016H
00018H
00020H
00022H
00024H
00026H
00028H
RESET input, POC, LVI, WDT,
TRAP
INTWDTI
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTST3
INTSR3
INTSRE3
INTDMA0
INTDMA1
INTST0/INTCSI00
INTSR0
INTSRE0
INTST1/INTCSI10/INTIIC10
INTSR1
INTSRE1
Interrupt Source
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17854EJ9V0UD
Table 3-3. Vector Table
Vector Table Address
0002AH
0002CH
0002EH
0003AH
0004AH
0004CH
0004EH
00030H
00032H
00034H
00036H
00038H
00042H
00044H
00046H
00048H
00050H
00052H
00054H
0007EH
INTIIC0
INTTM00
INTTM01
INTTM02
INTTM03
INTAD
INTRTC
INTRTCI
INTKR
INTTM04
INTTM05
INTTM06
INTTM07
INTP6
INTP7
INTP8
INTP9
INTP10
INTP11
BRK
Interrupt Source