UPD78F1144AGB-GAH-AX Renesas Electronics America, UPD78F1144AGB-GAH-AX Datasheet - Page 333

• Manufacturer Part Number: UPD78F1144AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1144AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(9) Interrupt request flag (ADIF)
(10) Conversion results just after A/D conversion start
(11) A/D conversion result register (ADCR, ADCRH) read operation
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Remarks 1. n = 0 to 7
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 1
conversion end interrupt request (INTAD) and removing the first conversion result.
When a write operation is performed to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may
become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion result to be read.
A/D conversion
ADCR
ADIF
2. m = 0 to 7
ADS rewrite
(start of ANIn conversion)
Figure 10-27. Timing of A/D Conversion End Interrupt Request Generation
ANIn
μ
s after the ADCE bit was set to 1 Take measures such as polling the A/D
CHAPTER 10 A/D CONVERTER
ADS rewrite
(start of ANIm conversion)
User’s Manual U17854EJ9V0UD
ANIn
ANIn
ANIm
ANIn
ADIF is set but ANIm conversion
has not ended.
ANIm
ANIm
ANIm
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