EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 136

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–32
Figure 5–26. Phase Relationship Between the PLL Clocks in External Feedback Mode for Arria II Devices
Note to
(1) The PLL clock outputs can lead or lag the fbin clock input.
Figure 5–27. External Feedback Mode in Arria II GZ Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
Clock Multiplication and Division
5–26:
inclk
Figure 5–26
clocks in external feedback mode.
Figure 5–27
Each Arria II PLL provides clock synthesis for PLL output ports with
M/(N × post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor (n) and is then multiplied by the m feedback factor. The control loop drives the
VCO to match f
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output frequencies
that meets its frequency specifications. For example, if output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz in the VCO range). Then the post-scale
counters scale down the VCO frequency for each output port.
÷n
PLL Reference
PLL Clock at
the Register
Clock Port (1)
Dedicated PLL
Clock Outputs (1)
fbin Clock Input Pin
Clock at the
Input Pin
shows an example waveform of the phase relationship between the PLL
shows external feedback mode implementation in Arria II GZ devices.
in
PFD
(M/N). Each output port has a unique post-scale counter that
Phase Aligned
CP/LF
VCO
÷C0
÷C1
÷m
Chapter 5: Clock Networks and PLLs in Arria II Devices
fbout
fbin
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
December 2010 Altera Corporation
external
board
trace
PLLs in Arria II Devices