EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 63

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Figure 3–17. True Dual-Port Timing Waveform
December 2010 Altera Corporation
q_a (asynch)
q_b (asynch)
address_a
address_b
wren_a
data_a
wren_b
Shift-Register Mode
clk_a
clk_b
din-1
an-1
doutn-1
Figure 3–17
and the read operation at port B with the read-during-write behavior set to new data.
Registering the RAM outputs delay the q outputs by one clock cycle.
All Arria II memory blocks support shift register mode. Embedded memory block
configurations can implement shift registers for digital signal processing (DSP)
applications, such as finite impulse response (FIR) filters, pseudo-random number
generators, multi-channel filtering, and auto- and cross-correlation functions. These
and other DSP applications require local data storage, traditionally implemented with
standard flipflops that quickly exhaust many logic cells for large shift registers. A
more efficient alternative is to use embedded memory as a shift-register block, which
saves logic cell and routing resources.
The size of a shift register (w × m × n) is determined by the input data width (w), the
length of the taps (m), and the number of taps (n). You can cascade memory blocks to
implement larger shift registers.
bn
din-1
din
an
shows true dual-port timing waveforms for the write operation at port A
doutn
din
b0
a0
dout0
a1
dout0
dout1
Arria II Device Handbook Volume 1: Device Interfaces and Integration
b1
a2
dout2
a3
dout3
dout1
b2
din4
a4
din4
din5
a5
dout2
din5
b3
din6
a6
3–17