EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 222

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

7–26
Figure 7–19. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry for Arria II GZ Devices
Notes to
(1) For possible reference input clock pins for each DLL, refer to
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DQS/CQ
DQS/CQ
CQn
CQn
Pin
Pin
Pin
Pin
Figure
7–19:
Δt
Δt
Δt
Δt
Phase-Shift
Phase-Shift
DQS phase-shift circuitry is connected to DQS logic blocks that control each DQS/CQ
or CQn pin. The DQS logic blocks allow the DQS delay settings to be updated
concurrently at every DQS/CQ or CQn pin.
Reference
Reference
Circuitry
Circuitry
Clock (2)
Clock (2)
DQS
DQS
DLL
DLL
IOE
IOE
IOE
IOE
to
to
to
to
to IOE
CQn
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
CQn
to IOE
Pin
Δt
“DLL” on page
DQS Logic
Blocks
to IOE
CQn
Pin
Δt
DQS/CQ
7–27.
to IOE
Pin
Δt
DQS/CQ
Chapter 7: External Memory Interfaces in Arria II Devices
to IOE
Pin
Δt
CQn
to IOE
Pin
Δt
Arria II External Memory Interface Features
Phase-Shift
Phase-Shift
Reference
Reference
Clock (2)
Clock (2)
Circuitry
Circuitry
(Note 1)
DLL
DQS
DQS
DLL
IOE
IOE
IOE
IOE
December 2010 Altera Corporation
to
to
to
to
DQS Logic
Blocks
Δt
Δt
Δt
Δt
DQS/CQ
DQS/CQ
CQn
CQn
Pin
Pin
Pin
Pin