EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 191

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: I/O Features in Arria II Devices
Termination Schemes for I/O Standards
December 2010 Altera Corporation
Differential LVPECL
Arria II devices support the LVPECL I/O standard on input clock pins only. LVPECL
output operation is not supported. LVDS input buffers are used to support LVPECL
input operation. AC-coupling is required when the LVPECL common mode voltage of
the output buffer is higher than Arria II LVPECL input common mode voltage.
Figure 6–16
receiver end are external to the device.
Figure 6–16. LVPECL AC-Coupled Termination
Arria II devices support DC-coupled LVPECL if the LVPECL output common mode
voltage is within the Arria II LVPECL input buffer specification (see
Figure 6–17. LVPECL DC-Coupled Termination
RSDS
Arria II devices supports true RSDS, RSDS with a one-resistor network, and RSDS
with a three-resistor network. Two single-ended output buffers are used for external
one- or three-resistor networks, as shown in
banks support RSDS output using true LVDS output buffers without an external
resistor network.
Output Buffer
Output Buffer
LVPECL
LVPECL
shows the AC-coupled termination scheme. The 50-Ω resistors used at the
0.1 μF
0.1 μF
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Z
Z
Z
Z
O
O
O
O
= 50 Ω
= 50 Ω
Figure
V
ICM
100 Ω
6–18. Only Arria II GZ row I/O
LVPECL Input Buffer
LVPECL Input Buffer
Arria II
Arria II
Figure
6–17).
6–33