EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 532

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–42
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric-Receiver Interface Clocking
The receiver phase compensation FIFO compensates for the phase difference between
the parallel receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO
read clock). The receiver phase compensation FIFO read clock forms the FPGA
fabric-receiver interface clock. The FIFO write and read clocks must have exactly the
same frequency, in other words, 0 PPM frequency difference.
Arria II GX and GZ transceivers provide the following two options for selecting the
receiver phase compensation FIFO read clock:
■
■
Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock
If you do not select the rx_coreclk port in the ALTGX MegaWizard Plug-In Manager,
the Quartus II software automatically selects the receiver phase compensation FIFO
read clock for each channel in that ALTGX instance. The Quartus II software selects
the FIFO read clock depending on the channel configuration.
Non-Bonded Channel Configuration with Rate Matcher
In the non-bonded channel configuration, the transceiver channels may or may not be
identical. Identical transceiver channels are defined as channels that have the same
CMU PLL and receiver CDR input reference clock source, have exactly the same CMU
PLL and receiver CDR configuration, and have exactly the same PMA and PCS
configuration.
Quartus II software-selected receiver phase compensation FIFO read clock
User-selected receiver phase compensation FIFO read clock
If all four channels within a transceiver block are identical, the Quartus II software
automatically drives the read port of the receiver phase compensation FIFO in all
four channels with tx_clkout[0], as shown in
signal to latch the receiver data and status signals from all four channels in the
FPGA fabric.
Example 6: Four Identical Channels in a Transceiver Block
Chapter 2: Transceiver Clocking in Arria II Devices
Figure
FPGA Fabric-Transceiver Interface Clocking
2–24. Use the tx_clkout[0]
December 2010 Altera Corporation