EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 473

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Arria II Devices
Test Modes
Figure 1–83. Reverse Serial Pre-CDR Loopback Datapath
Note to
(1) The only active block of the transmitter channel is the transmitter buffer.
December 2010 Altera Corporation
Fabric
FPGA
Figure
Reverse Serial Pre-CDR Loopback
1–83:
Reverse serial pre-CDR loopback is available in Basic functional mode only. In this
mode, the data received through the rx_datain port is looped back to the tx_dataout
port before the receiver CDR. The received data is also available to the FPGA logic.
You can enable the reverse serial pre-CDR loopback option using the ALTGX
MegaWizard Plug-In Manager. Unlike other loopback modes, there is no dynamic pin
control to enable or disable reverse serial pre-CDR loopback.
Figure 1–83
loopback mode.
You can change the V
Plug-In Manager. However, you cannot change the pre-emphasis settings for the
transmitter buffer.
tx_clkout[0]
Compensation
wrclk
shows the transceiver channel datapath for reverse serial pre-CDR
TX Phase
FIFO
rdclk
OD
on the transmitter buffer through the ALTGX MegaWizard
/2
wrclk
Byte Serializer
/2
Receiver Channel PCS
(Note 1)
Transmitter Channel PCS
rdclk
8B/10B Encoder
Arria II Device Handbook Volume 2: Transceivers
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Parallel Recovery Clock
High-Speed
Serial Clock
Transmitter Channel
Receiver Channel
PMA
Pre-CDR Loopback
Reverse Serial
PMA
1–87