EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 460
EP2AGX65DF29I5N
Manufacturer Part Number
EP2AGX65DF29I5N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX65DF29I5N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
EP2AGX65DF29I5N
Manufacturer:
ALTERA31
Quantity:
199
Part Number:
EP2AGX65DF29I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Arria II Device Handbook Volume 2: Transceivers
Serial Rapid I/O
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signal, communications and network processors, system memories, and
peripheral devices.
The Serial RapidIO physical layer specification defines three line rates—1.25 Gbps,
2.5 Gbps, and 3.125 Gbps. It also defines two link widths—single-lane (×1) and
bonded four-lane (×4) at each line rate. Arria II GX and GZ transceivers support only
single-lane (×1) configuration at all three line rates. You can instantiate four ×1
channels configured in Serial RapidIO mode to achieve one non-bonded ×4 Serial
RapidIO link. The four receiver channels in this ×4 Serial RapidIO link do not have
lane alignment or deskew capability.
Arria II GX and GZ transceivers, when configured in Serial RapidIO functional mode,
provide the following PCS and PMA functions:
■
■
■
■
■
Arria II GX and GZ transceivers do not have built-in support for some PCS functions,
such as pseudo-random idle sequence generation and lane alignment in ×4 mode.
Depending on your system requirements, you must implement these functions in the
logic array or external circuits.
8B/10B encoding and decoding
Word alignment
Lane synchronization state machine
Clock recovery from the encoded data
Serialization and deserialization
Chapter 1: Transceiver Architecture in Arria II Devices
December 2010 Altera Corporation
Functional Modes
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