EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 255

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Figure 8–11. Receiver Data Re-Alignment Rollover
Figure 8–12. Deserializer Bypass
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
December 2010 Altera Corporation
rx_divfwdclk
rx_outclock
rx_channel_data_align
Fabric
FPGA
rx_out
Figure
rx_cda_max
rx_outclock
rx_inclock
8–12:
2
Figure 8–11
signal pulses for one rx_outclock cycle to indicate that rollover has occurred.
Deserializer
The deserializer, which includes shift registers and parallel load registers, converts the
serial data from the bit slip to parallel data before sending the data to the FPGA fabric.
The deserialization factor supported is 4, 6, 7, 8, or 10. You can bypass the deserializer
to support DDR (×2) and SDR (×1) operations, as shown in
use the DPA and data realignment circuit when the deserializer is bypassed. The IOE
contains two data input registers that can operate in DDR or SDR mode.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
Deser
Deserializ
DOUT DIN
(Note
shows a preset value of 4-bit times before rollover occurs. The rx_cda_max
ializer
er
1), (2),
IOE
2
PLL (4)
PLL (4)
3
(3)
DOUT DIN
Multiplexer
Bit Slip
Clock
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
p
diffioclk
Arria II Device Handbook Volume 1: Device Interfaces and Integration
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Figure
DPA Circuitr
Retimed
DPA Cloc
Data
P P
P P
8–12. You cannot
k
DIN
y
+
rx_in
8–15