EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 416

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–30
Figure 1–31. Word Aligner
Arria II Device Handbook Volume 2: Transceivers
rx_enapatternalign
rx_revbitorderwa
rx_invpolarity
rx_a1a2size
Receiver PCS
rx_datain
rx_bitslip
f
1
This section describes the receiver PCS modules, which consist of the word aligner,
deskew FIFO, rate-match FIFO, 8B/10B decoder, byte deserializer, byte ordering, and
RX phase compensation FIFO.
The rx_digitalreset signal resets all modules in the receiver PCS block.
For more information about this signal, refer to the
Arria II Devices
Word Aligner
The word aligner receives parallel data from the deserializer and restores the word
boundary based on a pre-defined alignment pattern that must be received during link
synchronization.
Serial protocols such as GIGE, PCIe, Serial RapidIO, SONET/SDH, and XAUI specify
a standard word alignment pattern. The Arria II GX and GZ transceiver architecture
allows you to select a custom word alignment pattern specific to your implementation
if you use proprietary protocols.
Figure 1–31
In addition to restoring word boundaries, the word aligner also implements the
following features:
■
Programmable run length violation detection—This feature is available in all
functional modes. It detects consecutive 1s or 0s in the data stream. If a preset
maximum number of consecutive 1s or 0s is detected, the run length violation
status signal (rx_rlv) is asserted. This signal has lower latency when compared
with the parallel data on the rx_dataout port.
The rx_rlv signal in each channel is clocked by its parallel recovered clock and is
asserted for a minimum of two recovered clock cycles to ensure that the FPGA
fabric clock can latch the rx_rlv signal reliably because the FPGA fabric clock
might have phase differences, PPM differences (in asynchronous systems), or
both, with the recovered clock.
Receiver
Inversion
Polarity
shows the word aligner block diagram.
chapter.
Run Length Violation
Synchronization
Bit Slip Circuitry
State Machine
Alignment
Manual
Receiver
Reversal
Chapter 1: Transceiver Architecture in Arria II Devices
Bit
Word Aligner
Reset Control and Power Down in
December 2010 Altera Corporation
Data to Deskew FIFO
rx_bitslipboundaryselectout
rx_rlv
rx_syncstatus
rx_patterndetect
Receiver Channel Datapath