EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 478

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–92
Figure 1–88. Block Diagram of the Dynamic Reconfiguration Controller
Note to
(1) The PMA control ports consist of the V
Arria II Device Handbook Volume 2: Transceivers
rate_switch_ctrl[1:0] (TX only)
logical_channel_address[ ]
reset_reconfig_address
reconfig_mode_sel[2:0]
PMA control ports (1)
rx_tx_duplex_sel[1:0]
logical_tx_pll_sel_en
Figure
reconfig_fromgxb[ ]
reconfig_data[15:0]
logical_tx_pll_sel
reconfig_clk
1–88:
write_all
read
Each transceiver channel has multiple physical medium attachment controls that you
can program to achieve the desired bit error ratio (BER) for your system. When you
enable the dynamic reconfiguration feature, you can reconfigure the following
portions of each transceiver channel dynamically (one channel at a time) without
powering down the other transceiver channels or the FPGA fabric of the device:
■
■
■
■
The dynamic reconfiguration controller is a soft IP that uses FPGA-fabric resources.
You can use only one dynamic reconfiguration controller per transceiver block. You
cannot use the dynamic reconfiguration controller to control multiple Arria II GX and
GZ devices or off-chip interfaces.
dynamic reconfiguration controller architecture.
Transmit and receive analog settings
Transmit data rate in multiples of 1, 2, and 4
Channel and clock multiplier unit PLL
CMU PLL only
reconfiguration
reconfiguration
reconfiguration
TX PLL select
PMA controls
Control Logic
Channel and
Channel and
Cancellation
control logic
control logic
control logic
control logic
Data Rate
CMU PLL
CMU PLL
CMU PLL
OD
Switch
Offset
logic
controls, pre-emphasis controls, DC gain controls, and manual equalization controls.
Figure 1–88
Translation
Address
Chapter 1: Transceiver Architecture in Arria II Devices
shows the conceptual view of the
addr
data
Parallel to
Converter
Serial
December 2010 Altera Corporation
Dynamic Reconfiguration
reconfig_togxb[3:0]
data valid
busy
error
rate_switch_out[1:0] (TX only)
reconfig_address_out[5:0]
reconfig_address_en
channel_reconfig_done