EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 309

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
PS Configuration
Figure 9–13. PS Configuration Timing Waveform
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
(2) After power-up, the Arria II device holds nSTATUS low for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Two DCLK falling edges are required after CONF_DONE goes high to begin initialization of the device.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) For Arria II GX devices, DATA[0]is a dedicated pin that is used for both PS and AS configuration modes and is not available as a user I/O pin after
Table 9–12. PS Timing Parameters for Arria II Devices (Part 1 of 2)—Preliminary
December 2010 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
(1)
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
Symbol
nCONFIG is pulled low, a reconfiguration cycle begins.
configuration. For Arria II GZ devices, DATA[0] is available as a user I/O pin after configuration.
Figure
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
9–13:
CONF_DONE (3)
nSTATUS (2)
INIT_DONE
nCONFIG
PS Configuration Timing
Figure 9–13
device or microprocessor as an external host.
Table 9–12
User I/O
DCLK
DATA
t
t
CFG
CF2CD
lists the timing parameters for Arria II devices for PS configuration.
Parameter
shows the timing waveform for a PS configuration when using a MAX II
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
(Note 1)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Bit n
(4)
Minimum
500
3.2
3.2
—
—
10
—
2
2
4
0
8
t
CD2UM
Maximum
800
500
500
800
—
—
—
—
—
—
—
—
User Mode
(6)
(5)
(2)
(2)
(2)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9–29