EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 546

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–56
FPGA Fabric PLL-Transceiver PLL Cascading
Table 2–16. Allowed Input Reference Clock Frequencies for Example 11 for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Multiplication Factor (M)
Note to
(1) Violates the PFD frequency limit of 325 MHz.
Table
Dedicated Left PLL Cascade Lines Network
10
16
20
25
2–16:
2
4
5
8
The CMU PLL synthesizes the input reference clock to generate the high-speed serial
clock used in the transmitter PMA. The receiver CDR synthesizes the input reference
clock in lock-to-reference mode to generate the high-speed serial clock.
This high-speed serial clock output from the CMU PLL and receiver CDR runs at a
frequency that is half the configured data rate. The CMU PLLs and receiver CDRs
support multiplication factors (M) of 2, 4, 5, 8, 10, 16, 20, and 25. If you use an
on-board crystal oscillator to provide the input reference clock through the dedicated
REFCLK pins or ITB lines, the allowed crystal frequencies are limited by the CMU PLL
and receiver CDR multiplication factors. The input reference clock frequencies are
also limited by the allowed phase frequency detector (PFD) frequency range between
50 MHz and 325 MHz.
For a 3 Gbps data rate, the Quartus II software allows an input reference clock
frequency of 60, 75, 93.75, 150, 187.5, 300, 375, and 750 MHz. To overcome this
limitation, Arria II GX and GZ devices allow the synthesized clock output from left
corner PLLs in the FPGA fabric to drive the CMU PLL and receiver CDR input
reference clock. The additional clock multiplication factors available in the left corner
PLLs allow more options for on-board crystal oscillator frequencies.
Arria II GX devices have a dedicated PLL cascade network on the left side of the
device that connects to the input reference clock selection circuitry of the CMU PLLs
and receiver CDRs. The dedicated PLL cascade network on the left side of the device
connects to the input reference clock selection circuitry of the CMU PLLs and receiver
CDRs in transceiver blocks located on the left side of the device.
For a channel configured for 3 Gbps data rate, the high-speed serial clock output
from the CMU PLL and receiver CDR must run at 1.5 Gbps.
allowed input reference clock frequencies for Example 11.
Example 11: Channel Configuration for 3 Gbps Data Rate
On-Board Crystal Reference Clock Frequency (MHz)
with /N = 1
187.5
93.75
750
375
300
150
75
60
Chapter 2: Transceiver Clocking in Arria II Devices
With /N = 2
187.5
1500
750
600
375
300
150
120
FPGA Fabric PLL-Transceiver PLL Cascading
December 2010 Altera Corporation
Table 2–16
Allowed
lists the
No
No
Yes
Yes
Yes
Yes
Yes
Yes
(1)
(1)