EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 559

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

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AIIGX52003-3.0
Transceiver PLL Configurations
Arria II Device Handbook Volume 2: Transceivers
December 2010
December 2010
AIIGX52003-3.0
This chapter describes the configuration of multiple protocols and data rates for
Arria
can run at an independent data rate or protocol mode. Within each transceiver
channel, the transmitter and receiver channel can run at different data rates. Each
transceiver block consists of two clock multiplier unit (CMU) phase-locked loops
(PLLs) that provide clocks to all the transmitter channels within the transceiver block.
Each receiver channel contains a dedicated clock data recovery (CDR).
This chapter includes the following sections:
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You can configure each transmitter channel to use one of the two CMU PLLs in the
transceiver block. In addition, each transmitter channel has a local divider (/1, /2,
or /4) that divides the clock output of the CMU PLL to provide high-speed serial and
low-speed parallel clocks for its physical coding sublayer (PCS) and physical medium
attachment (PMA) functional blocks.
You can configure the RX CDR present in the receiver channel to a distinct data rate
and provide separate input reference clocks. Each receiver channel also contains a
local divider that divides the high-speed clock output of the RX CDR and provides
clocks for its PCS and PMA functional blocks. To enable transceiver channel settings,
the Quartus
interface. The ALTGX MegaWizard Plug-In Manager allows you to instantiate a single
transceiver channel or multiple transceiver channels in Receiver and Transmitter,
Receiver Only, and Transmitter Only configurations.
“Transceiver PLL Configurations” on page 3–1
“Creating Transceiver Channel Instances” on page 3–2
“General Requirements to Combine Channels” on page 3–2
“Sharing CMU PLLs” on page 3–3
“Combining Receiver Only Channels” on page 3–8
“Combining Transmitter Channel and Receiver Channel Instances” on page 3–9
“Combining Channels Configured in Protocol Functional Modes” on page 3–10
“Combining Transceiver Instances Using PLL Cascade Clocks” on page 3–12
“Combining Transceiver Instances in Multiple Transceiver Blocks” on page 3–13
“Summary” on page 3–15
®
II GX and GZ devices. Each transceiver channel in an Arria II GX or GZ device
®
II software provides the ALTGX MegaWizard
3. Configuring Multiple Protocols and
Data Rates in Arria II Devices
™
Plug-In Manager
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