EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 572

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

3–14
Arria II Device Handbook Volume 2: Transceivers
1
Figure 3–5
Figure 3–5. Transceiver Channel Instances before Compilation for Example 4
Figure 3–6
Figure 3–6. Combined Transceiver Instances after Compilation for Example 4
You can force the placement of the transceiver channels in specific transceiver banks
by assigning pins to the tx_dataout and rx_datain ports of inst0 and inst1.
Ch1 of inst0
Effective Data Rate: 3.125 Gbps
Ch0 of inst0
Effective Data Rate: 3.125 Gbps
Effective Data Rate: 3.125 Gbps
Ch3 of inst0
Effective Data Rate: 3.125 Gbps
Ch2 of inst0
shows the transceiver instances before compilation for Example 4.
shows the transceiver instances after compilation for Example 4.
Transceiver Block 0
Base Data Rate:
3.125 Gbps
CMU PLL
Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
Effective Data Rate: 3.125 Gbps
Input Clock Frequency: 156.125 MHz
Number of Channels: 7
Effective Data Rate: 3.125 Gbps
Input Clock Frequency: 156.25 MHz
Number of Channels: 1
Inst0
Inst1
Combining Transceiver Instances in Multiple Transceiver Blocks
Effective Data Rate: 3.125 Gbps
Effective Data Rate: 3.125 Gbps
Ch5 of inst0
Ch4 of inst0
Ch0 of inst1
Effective Data Rate: 3.125 Gbps
Ch6 of inst0
Effective Data Rate: 3.125 Gbps
Transceiver Block 1
Base Data Rate:
3.125 Gbps
December 2010 Altera Corporation
CMU PLL