EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 45

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
December 2010 Altera Corporation
ALM Interconnects
Clear and Preset Logic Control
LAB Power Management Techniques
There are three dedicated paths between ALMs: Register Cascade, Carry-chain, and
Shared Arithmetic chain. Arria II devices include an enhanced interconnect structure
in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic
functions. The register chain connection allows the register output of one ALM to
connect directly to the register input of the next ALM in the LAB for fast shift
registers. These ALM-to-ALM connections bypass the local interconnect.
shows the shared arithmetic chain, carry chain, and register chain interconnects.
Figure 2–15. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
LAB-wide signals control the logic for the register‘s clear signal. The ALM directly
supports an asynchronous clear function. You can achieve the register preset through
the Quartus II software’s NOT-gate push-back logic option. Each LAB supports up to
two clears.
Arria II devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in
the device. An option set before compilation in the Quartus II software enables this
pin. This device-wide reset overrides all other control signals.
The following techniques are used to manage static and dynamic power consumption
within the LAB:
■
■
The Quartus II software forces all adder inputs low when ALM adders are not in
use to save AC power.
Arria II LABs operate in high-performance mode or low-power mode. The
Quartus II software automatically chooses the appropriate mode for the LAB,
based on the design, to optimize speed versus leakage trade-offs.
routing to adjacent ALM
Carry chain & shared
arithmetic chain
interconnect
Local
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Local interconnect
routing among ALMs
in the LAB
ALM 10
ALM 1
ALM 2
ALM 3
Register chain
routing to adjacent
ALM's register input
Figure 2–15
2–17