EP2AGX65DF29I5N Altera, EP2AGX65DF29I5N Datasheet - Page 464

• Manufacturer Part Number: EP2AGX65DF29I5N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29I5N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–78
Arria II Device Handbook Volume 2: Transceivers
1
Unlike Ethernet, where the LSB of the parallel data byte is transferred first,
SONET/SDH requires the MSB to be transferred first. To facilitate the MSB-to-LSB
transfer, you must enable the Flip Transmitter input data bits and Flip Receiver
output data bits options in the ALTGX MegaWizard Plug-In Manager.
Depending on whether data bytes are transferred MSB-to-LSB or LSB-to-MSB, you
must select the appropriate word aligner settings in the ALTGX MegaWizard Plug-In
Manager.
Word Aligner in SONET/SDH Mode
The word aligner in SONET/SDH functional mode is configured in manual
alignment mode. You can configure the word aligner to either align to a 16-bit A1A2
pattern or a 32-bit A1A1A2A2 pattern, controlled by the rx_a1a2size input port to the
transceiver.
A low level on the rx_a1a2size port configures the word aligner to align to a 16-bit
A1A2 pattern; a high level configures the word aligner to align to a 32-bit A1A1A2A2
pattern.
In OC-96 configurations, the word aligner is only allowed to align to an A1A1A2A2
pattern, so the input port rx_ala2size is unavailable. Barring this difference, the
OC-96 word alignment operation is similar to that of the OC-12 and OC-48
configurations.
You can also configure the word aligner to flip the word alignment pattern bits
programmed in the ALTGX MegaWizard Plug-In Manager and compare them with
the incoming data for alignment. This feature offers flexibility to the SONET
backplane system for either a MSB-to-LSB or LSB-to-MSB data transfer.
lists word alignment patterns that you must program in the ALTGX MegaWizard
Plug-In Manager based on the bit-transmission order and the word aligner bit-flip
option.
Table 1–21. Word Aligner Settings for Arria II Devices
OC-48 and OC-96 Byte Serializer and Deserializer
The OC-48 and OC-96 transceiver datapath includes the byte serializer and
deserializer to allow the PLD interface to run at a lower speed. The OC-12
configuration does not use the byte serializer and deserializer blocks. The byte
serializer and deserializer blocks are explained in
“Byte Deserializer” on page
The OC-48 byte serializer converts 16-bit data words from the FPGA fabric and
translates the 16-bit data words into two 8-bit data bytes at twice the rate. The OC-48
byte deserializer takes in two consecutive 8-bit data bytes and translates them into a
16-bit data word to the FPGA fabric at half the rate.
Serial Bit Transmission Order
MSB-to-LSB
MSB-to-LSB
LSB-to-MSB
1–43, respectively.
Flip the Word Alignment
Pattern Bits
Off
Off
On
Chapter 1: Transceiver Architecture in Arria II Devices
“Byte Serializer” on page 1–14
Word Alignment Pattern
December 2010 Altera Corporation
16'hF628
16'h146F
16'h28F6
Table 1–21
Functional Modes
and